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Fri, 22 Nov 2024 08:40:12 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AM8eBsF010407 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Nov 2024 08:40:11 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 22 Nov 2024 00:40:07 -0800 Date: Fri, 22 Nov 2024 16:40:02 +0800 From: Yuanjie Yang To: Krzysztof Kozlowski , , , , , , , CC: , , , , , Subject: Re: [PATCH v3 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2 Message-ID: References: <20241122065101.1918470-1-quic_yuanjiey@quicinc.com> <20241122065101.1918470-2-quic_yuanjiey@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: O0RpfHuaPG2PlL20SvBDoP4UBuWkB1MH X-Proofpoint-ORIG-GUID: O0RpfHuaPG2PlL20SvBDoP4UBuWkB1MH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 clxscore=1011 impostorscore=0 suspectscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411220072 On Fri, Nov 22, 2024 at 08:04:31AM +0100, Krzysztof Kozlowski wrote: > On 22/11/2024 07:51, Yuanjie Yang wrote: > > Add SDHC1 and SDHC2 support to the QCS615 Ride platform. > > > > Signed-off-by: Yuanjie Yang > > --- > > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ > > 1 file changed, 198 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > > index 590beb37f441..37c6ab217c96 100644 > > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > > @@ -399,6 +399,65 @@ qfprom: efuse@780000 { > > #size-cells = <1>; > > }; > > > > + sdhc_1: mmc@7c4000 { > > + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; > > + reg = <0x0 0x007c4000 0x0 0x1000>, > > + <0x0 0x007c5000 0x0 0x1000>; > > + reg-names = "hc", > > + "cqhci"; > > + > > + interrupts = , > > + ; > > + interrupt-names = "hc_irq", > > + "pwr_irq"; > > + > > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > > + <&gcc GCC_SDCC1_APPS_CLK>, > > + <&rpmhcc RPMH_CXO_CLK>, > > + <&gcc GCC_SDCC1_ICE_CORE_CLK>; > > + clock-names = "iface", > > + "core", > > + "xo", > > + "ice"; > > + > > + resets = <&gcc GCC_SDCC1_BCR>; > > + > > + power-domains = <&rpmhpd RPMHPD_CX>; > > + operating-points-v2 = <&sdhc1_opp_table>; > > + iommus = <&apps_smmu 0x02c0 0x0>; > > + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; > > + interconnect-names = "sdhc-ddr", > > + "cpu-sdhc"; > > + > > + bus-width = <8>; > > + qcom,dll-config = <0x000f642c>; > > + qcom,ddr-config = <0x80040868>; > > + supports-cqe; > > + dma-coherent; > > + mmc-ddr-1_8v; > > + mmc-hs200-1_8v; > > + mmc-hs400-1_8v; > > + mmc-hs400-enhanced-strobe; > > These are properties of memory, not SoC. If the node is disabled, means > memory is not attached to the SoC, right? > > > + status = "disabled"; Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc, they are memory configurations that need to be written to the ioaddr. And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config, they indicate the bus speed at which the host contoller can operate. If the node is disabled, which means Soc don't support these properties. > > > ... > > > + > > + sdhc_2: mmc@8804000 { > > + compatible = "qcom,qcs615-sdhci","qcom,sdhci-msm-v5"; > > + reg = <0x0 0x08804000 0x0 0x1000>; > > + reg-names = "hc"; > > + > > + interrupts = , > > + ; > > + interrupt-names = "hc_irq", > > + "pwr_irq"; > > + > > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, > > + <&gcc GCC_SDCC2_APPS_CLK>, > > + <&rpmhcc RPMH_CXO_CLK>; > > + clock-names = "iface", > > + "core", > > + "xo"; > > + > > + power-domains = <&rpmhpd RPMHPD_CX>; > > + operating-points-v2 = <&sdhc2_opp_table>; > > + iommus = <&apps_smmu 0x02a0 0x0>; > > + resets = <&gcc GCC_SDCC2_BCR>; > > + interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > > + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; > > + interconnect-names = "sdhc-ddr", > > + "cpu-sdhc"; > > + > > + bus-width = <4>; > > Same comments. Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc, they are memory configurations that need to be written to the ioaddr. And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config, they indicate the bus speed at which the host controller can operate. If the node is disabled, which means Soc don't support these properties. > > + qcom,dll-config = <0x0007642c>; > > + qcom,ddr-config = <0x80040868>; > > + dma-coherent; > > + status = "disabled"; > > + > > + sdhc2_opp_table: opp-table { > > + compatible = "operating-points-v2"; > > + > > + opp-100000000 { > > + opp-hz = /bits/ 64 <100000000>; > > + required-opps = <&rpmhpd_opp_low_svs>; > > + }; > > + > > + opp-202000000 { > > + opp-hz = /bits/ 64 <202000000>; > > + required-opps = <&rpmhpd_opp_nom>; > > + }; > > + }; > > }; > > > > dc_noc: interconnect@9160000 { > > > Best regards, > Krzysztof Thanks, Yuanjie