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Mon, 25 Nov 2024 08:52:41 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AP8qeAT011133 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Nov 2024 08:52:40 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 25 Nov 2024 00:52:36 -0800 Date: Mon, 25 Nov 2024 16:52:31 +0800 From: Yuanjie Yang To: Krzysztof Kozlowski , , , , , , , CC: , , , , , Subject: Re: [PATCH v3 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2 Message-ID: References: <20241122065101.1918470-1-quic_yuanjiey@quicinc.com> <20241122065101.1918470-2-quic_yuanjiey@quicinc.com> <97a6c471-b146-4625-a3fa-93ee29be4c37@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _QsxndKFC_mgH13EdVghEKKWy53Z6uUZ X-Proofpoint-GUID: _QsxndKFC_mgH13EdVghEKKWy53Z6uUZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 bulkscore=0 adultscore=0 mlxscore=0 mlxlogscore=999 clxscore=1015 phishscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411250075 On Mon, Nov 25, 2024 at 09:16:02AM +0100, Krzysztof Kozlowski wrote: > On 25/11/2024 09:06, Yuanjie Yang wrote: > >>>>>>> + > >>>>>>> + resets = <&gcc GCC_SDCC1_BCR>; > >>>>>>> + > >>>>>>> + power-domains = <&rpmhpd RPMHPD_CX>; > >>>>>>> + operating-points-v2 = <&sdhc1_opp_table>; > >>>>>>> + iommus = <&apps_smmu 0x02c0 0x0>; > >>>>>>> + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS > >>>>>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > >>>>>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > >>>>>>> + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; > >>>>>>> + interconnect-names = "sdhc-ddr", > >>>>>>> + "cpu-sdhc"; > >>>>>>> + > >>>>>>> + bus-width = <8>; > >>>>>>> + qcom,dll-config = <0x000f642c>; > >>>>>>> + qcom,ddr-config = <0x80040868>; > >>>>>>> + supports-cqe; > >>>>>>> + dma-coherent; > >>>>>>> + mmc-ddr-1_8v; > >>>>>>> + mmc-hs200-1_8v; > >>>>>>> + mmc-hs400-1_8v; > >>>>>>> + mmc-hs400-enhanced-strobe; > >>>>>> > >>>>>> These are properties of memory, not SoC. If the node is disabled, means > >>>>>> memory is not attached to the SoC, right? > >>>>>> > >>>>>>> + status = "disabled"; > >>>>> Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc, > >>>>> they are memory configurations that need to be written to the ioaddr. > >>>>> And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config, > >>>>> they indicate the bus speed at which the host contoller can operate. > >>>>> If the node is disabled, which means Soc don't support these properties. > >>>> No, that is not the meaning of node is disabled. When node is disabled, > >>>> it means board does not have attached memory. > >>>> > >>>> Move the memory related properties to the board. > >>> > >>> Thanks, Ok I understand, I will move the memory related > >>> properties(qcom,dll-config and qcom,ddr-config) to the > >>> board dts in next version. > >> > >> What? Why are you talking about these properties? My comment was not > >> under these! > > Thanks, Sorry, I may have misunderstood your meaning. > > Do you mean I need move memory realted properties(bus-width, dma-coherent) > > to the board dts? > > When this node's status is okay, then board can set these memory config. > > I will fix it in next version. > > Keep all discussions public. Where was my comment? Under dma-coherent? > No. Each comment is in very specific place. I asked about memory > specific properties. > > I also rephrased it differently already, but maybe not clear enough: you > cannot have here properties which are not properties of the SoC. > > I am not going to discuss it more in private. Read the netiquette. > > https://people.kernel.org/tglx/notes-about-netiquette Thanks, Sorry, I accidentally sent the email just now; I didn't mean to send it privately. Ok, I agree with your idea. properties which are not of Soc should move to board dts. I double check my dts, dtsi. I think I should move properties(bus-width, mmc-ddr-1_8v, mmc-hs200-1_8v, mmc-hs400-1_8v, mmc-hs400-enhanced-strobe) to board dts, these properties are just to config Soc. Do you agree my option? Thanks again for your time to point out my mistake. > Best regards, > Krzysztof Thanks, Yuanjie