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Tue, 26 Nov 2024 09:12:05 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AQ9C1i1007065 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 26 Nov 2024 09:12:02 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 26 Nov 2024 01:11:57 -0800 Date: Tue, 26 Nov 2024 17:11:53 +0800 From: Yuanjie Yang To: Konrad Dybcio , , , , , , , CC: , , , , , Subject: Re: [PATCH v3 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2 Message-ID: References: <20241122065101.1918470-1-quic_yuanjiey@quicinc.com> <20241122065101.1918470-2-quic_yuanjiey@quicinc.com> <7c0c1120-c2b2-40dd-8032-339cc4d4cda4@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: uZbjmKjYUsmvQQXFba7ESStf18Yq8LOp X-Proofpoint-ORIG-GUID: uZbjmKjYUsmvQQXFba7ESStf18Yq8LOp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 clxscore=1015 phishscore=0 spamscore=0 adultscore=0 impostorscore=0 mlxscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411260072 On Tue, Nov 26, 2024 at 05:07:11PM +0800, Yuanjie Yang wrote: > On Mon, Nov 25, 2024 at 02:13:22PM +0100, Konrad Dybcio wrote: > > On 22.11.2024 7:51 AM, Yuanjie Yang wrote: > > > Add SDHC1 and SDHC2 support to the QCS615 Ride platform. > > > > > > Signed-off-by: Yuanjie Yang > > > --- > > > arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ > > > 1 file changed, 198 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > > > index 590beb37f441..37c6ab217c96 100644 > > > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > > > @@ -399,6 +399,65 @@ qfprom: efuse@780000 { > > > #size-cells = <1>; > > > }; > > > > > > + sdhc_1: mmc@7c4000 { > > > + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; > > > + reg = <0x0 0x007c4000 0x0 0x1000>, > > > + <0x0 0x007c5000 0x0 0x1000>; > > > + reg-names = "hc", > > > + "cqhci"; > > > > There's an "ice" region at 0x007c8000 > Thanks, I check doc again, I miss "ice" region at 0x007c8000. > > > > + > > > + interrupts = , > > > + ; > > > + interrupt-names = "hc_irq", > > > + "pwr_irq"; > > > + > > > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > > > + <&gcc GCC_SDCC1_APPS_CLK>, > > > + <&rpmhcc RPMH_CXO_CLK>, > > > + <&gcc GCC_SDCC1_ICE_CORE_CLK>; > > > + clock-names = "iface", > > > + "core", > > > + "xo", > > > + "ice"; > > > + > > > + resets = <&gcc GCC_SDCC1_BCR>; > > > + > > > + power-domains = <&rpmhpd RPMHPD_CX>; > > > + operating-points-v2 = <&sdhc1_opp_table>; > > > + iommus = <&apps_smmu 0x02c0 0x0>; > > > + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS > > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > > > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; > > > + interconnect-names = "sdhc-ddr", > > > + "cpu-sdhc"; > > > + > > > + bus-width = <8>; > > > + qcom,dll-config = <0x000f642c>; > > > + qcom,ddr-config = <0x80040868>; > > > + supports-cqe; > > > + dma-coherent; > > > + mmc-ddr-1_8v; > > > + mmc-hs200-1_8v; > > > + mmc-hs400-1_8v; > > > + mmc-hs400-enhanced-strobe; > > > + status = "disabled"; > > > + > > > + sdhc1_opp_table: opp-table { > > > + compatible = "operating-points-v2"; > > > + > > > + opp-100000000 { > > > + opp-hz = /bits/ 64 <100000000>; > > > + required-opps = <&rpmhpd_opp_svs>; > > > + }; > > > > I'm seeing 25/50 MHz OPPs in the docs as well > Thanks, I check doc again, I miss 50MHz OPPs, but I don't find 25MHz. > > > [...] > > > > > + > > > + sdhc_2: mmc@8804000 { > > > + compatible = "qcom,qcs615-sdhci","qcom,sdhci-msm-v5"; > > > > Missing space Thanks, I will add space in next version. > > > + reg = <0x0 0x08804000 0x0 0x1000>; > > > + reg-names = "hc"; > > > + > > > + interrupts = , > > > + ; > > > + interrupt-names = "hc_irq", > > > + "pwr_irq"; > > > + > > > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, > > > + <&gcc GCC_SDCC2_APPS_CLK>, > > > + <&rpmhcc RPMH_CXO_CLK>; > > > + clock-names = "iface", > > > + "core", > > > + "xo"; > > > + > > > + power-domains = <&rpmhpd RPMHPD_CX>; > > > + operating-points-v2 = <&sdhc2_opp_table>; > > > + iommus = <&apps_smmu 0x02a0 0x0>; > > > + resets = <&gcc GCC_SDCC2_BCR>; > > > + interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS > > > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > > > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > > > + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; > > > + interconnect-names = "sdhc-ddr", > > > + "cpu-sdhc"; > > > + > > > + bus-width = <4>; > > > + qcom,dll-config = <0x0007642c>; > > > + qcom,ddr-config = <0x80040868>; > > > + dma-coherent; > > > + status = "disabled"; > > > + > > > + sdhc2_opp_table: opp-table { > > > + compatible = "operating-points-v2"; > > > + > > > > Similarly, it can operate at 25/50 MHz too > Thanks, I check doc again, I miss 50MHz OPPs, but I don't find 25MHz. > > > > > Konrad > > Thanks, > Yuanjie > Thanks, Yuanjie