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Tue, 10 Dec 2024 09:24:39 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BA9ObmM028576 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 10 Dec 2024 09:24:37 GMT Received: from hu-wasimn-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 10 Dec 2024 01:24:30 -0800 Date: Tue, 10 Dec 2024 14:54:22 +0530 From: Wasim Nazir To: Krzysztof Kozlowski CC: Dmitry Baryshkov , Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Subject: Re: [PATCH v3 5/5] arm64: dts: qcom: Add support for QCS9075 Ride & Ride-r3 Message-ID: References: <20241119174954.1219002-1-quic_wasimn@quicinc.com> <20241119174954.1219002-6-quic_wasimn@quicinc.com> <9e351979-be01-4d38-9b94-cc23efac4c3f@kernel.org> <8cf9edc0-a0cb-4fd0-b10e-2138784dfba3@kernel.org> <5782d7c6-1a75-4f15-8942-387742e0ae09@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <5782d7c6-1a75-4f15-8942-387742e0ae09@kernel.org> X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 9rMVKJ6zcSB1_APun9m_PZObBHhyzWVl X-Proofpoint-GUID: 9rMVKJ6zcSB1_APun9m_PZObBHhyzWVl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 adultscore=0 mlxlogscore=644 clxscore=1015 spamscore=0 mlxscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412100069 On Tue, Dec 10, 2024 at 08:25:34AM +0100, Krzysztof Kozlowski wrote: > On 10/12/2024 00:25, Dmitry Baryshkov wrote: > >>>>>> 9100 & 9075 are different from “safe” perspective. They differ in > >>>>>> changes related to thermal which will be added later in devicetree. > >>>>> > >>>>> Since this can't be inferred from just looking at the changes, please > >>>>> make sure to add that to the commit message > >>>> > >>>> Any include of other DTS is clear sign something is odd here. Including > >>>> multiple times without any added nodes is showing these are not real > >>>> products/boards . > >>> > >>> We're adding DTS to reuse the common board changes, with plans to > >>> include the differences in upcoming patches. To provide more clarity, I > >>> will include patches in this series to highlight the differences between > >>> the 9100 and 9075 boards. > >> > >> Sure, still do not include DTS. Just like C files don't include C files. > > > > So, is the solution simple, rename .dts to .dtsi and include it from > > both .dts files? > > For example. This leads to more questions - what is common here? We do > not create shared DTSI files just because someone wants, but to really > note shared components or shared designs. > We can reuse the common dtsi for ride boards, i.e., sa8775p-ride.dtsi, and then add board-specific changes in the corresponding files. If this approach is acceptable, I can proceed with sending the next patch series. I hope this will help clarify things further. > Best regards, > Krzysztof Thanks & Regards, Wasim