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Fri, 03 Jan 2025 06:53:01 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5036r0t2012610 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 3 Jan 2025 06:53:00 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 2 Jan 2025 22:52:55 -0800 Date: Fri, 3 Jan 2025 12:22:51 +0530 From: Varadarajan Narayanan To: Manikanta Mylavarapu CC: , , , , , , , , , , , , , , , , Subject: Re: [PATCH 4/4] arm64: dts: qcom: ipq5424: Enable PCIe PHYs and controllers Message-ID: References: <20241213134950.234946-1-quic_mmanikan@quicinc.com> <20241213134950.234946-5-quic_mmanikan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20241213134950.234946-5-quic_mmanikan@quicinc.com> X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: lT6gXrGBlZrGDdzVkjHQ1dyfzH1S9LgO X-Proofpoint-GUID: lT6gXrGBlZrGDdzVkjHQ1dyfzH1S9LgO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 adultscore=0 spamscore=0 malwarescore=0 clxscore=1015 suspectscore=0 phishscore=0 mlxlogscore=614 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501030058 On Fri, Dec 13, 2024 at 07:19:50PM +0530, Manikanta Mylavarapu wrote: [ . . . ] > +&pcie2_phy { > + status = "okay"; > +}; > + > +&pcie2 { > + pinctrl-0 = <&pcie2_default_state>; > + pinctrl-names = "default"; > + > + perst-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; > + status = "okay"; > +}; pcie2 should come before pcie2_phy > + > +&pcie3_phy { > + status = "okay"; > +}; > + > +&pcie3 { > + pinctrl-0 = <&pcie3_default_state>; > + pinctrl-names = "default"; > + > + perst-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; > + status = "okay"; > +}; same here. -Varada