Re: [PATCH 10/12] dt-bindings: usb: qcom,dwc3: Introduce flattened qcom,dwc3 binding

Johan Hovold
2023-11-22T12:40:30Z

On Mon, Oct 16, 2023 at 08:11:18PM -0700, Bjorn Andersson wrote:
> The Qualcomm USB block consists of three intertwined parts, the XHCI,
> the DWC3 core and the Qualcomm DWC3 glue. The three parts can not be
> operated independently, but the binding was for historical reasons split
> to mimic the Linux driver implementation.
>
> The split binding also makes it hard to alter the implementation, as
> properties and resources are split between the two nodes, in some cases
> with some duplication.
>
> Introduce a new binding, with a single representation of the whole USB
> block in one node.
>
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>

> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc8280xp-dwc3
> + - qcom,sc8280xp-dwc3-mp

The multiport implementation is not ready yet and this part of the
binding has been reverted (similar for the multiport interrupts below).

> + then:
> + properties:
> + clocks:
> + maxItems: 9
> + clock-names:
> + items:
> + - const: cfg_noc
> + - const: core
> + - const: iface
> + - const: sleep
> + - const: mock_utmi
> + - const: noc_aggr
> + - const: noc_aggr_north
> + - const: noc_aggr_south
> + - const: noc_sys

> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,sc8280xp-dwc3-mp
> + then:
> + properties:
> + interrupts:
> + maxItems: 14
> + interrupt-names:
> + items:
> + - const: pwr_event_1
> + - const: pwr_event_2
> + - const: pwr_event_3
> + - const: pwr_event_4
> + - const: dp_hs_phy_1
> + - const: dm_hs_phy_1
> + - const: dp_hs_phy_2
> + - const: dm_hs_phy_2
> + - const: dp_hs_phy_3
> + - const: dm_hs_phy_3
> + - const: dp_hs_phy_4
> + - const: dm_hs_phy_4
> + - const: ss_phy_1
> + - const: ss_phy_2

So same here.

> + else:
> + properties:
> + interrupts:
> + minItems: 1
> + items:
> + - description: Common DWC3 interrupt
> + - description: The interrupt that is asserted
> + when a wakeup event is received on USB2 bus.
> + - description: The interrupt that is asserted
> + when a wakeup event is received on USB3 bus.
> + - description: Wakeup event on DM line.
> + - description: Wakeup event on DP line.

I guess you may have copied this from the current binding but the
descriptions here are not correct. The HS/SS interrupt comes from the
PHYs in case the corresponding events have been enabled. I assume it can
be used for connect/disconnect events as well as remote wakeup and
whether to actually wake the system up on those is an implementation
detail.

Similar for DM/DP which represents the state of the data lines and that
can be used to detect all sorts of events, not just remote wakeup.

> +
> + interrupt-names:
> + minItems: 1
> + items:
> + - const: dwc_usb3
> + - const: hs_phy_irq
> + - const: ss_phy_irq
> + - const: dm_hs_phy_irq
> + - const: dp_hs_phy_irq

And here you are now defining all of these interrupts for all the
current SoCs it seems, despite not all of them actually having all of
these at once. (The order also does not match the current devicetrees.)

Some only have HS/SS, and it's not clear whether the HS interrupts are
actually functional when a SoC is also using DP/DM.

We're currently discussing this here:

https://lore.kernel.org/lkml/ZVYTFi3Jnnljl48L@hovoldconsulting.com/

> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + usb@a600000 {
> + compatible = "qcom,sdm845-dwc3", "qcom,dwc3", "snps,dwc3";
> + reg = <0x0a600000 0x200000>;

> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
> + phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> + phy-names = "usb2-phy", "usb3-phy";
> +

Stray newline.

> + };
> +...

Johan