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X-CSE-ConnectionGUID: w1P2X7QDTUqALWkDM+VFxQ== X-CSE-MsgGUID: eD54R3SET1K2TwqA0vLKcg== X-IronPort-AV: E=McAfee;i="6700,10204,11242"; a="55575487" X-IronPort-AV: E=Sophos;i="6.11,247,1725346800"; d="scan'208";a="55575487" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2024 14:05:24 -0700 X-CSE-ConnectionGUID: 5foGy5bPQLqQElX3moR8kA== X-CSE-MsgGUID: EkRWfefLSq27SEFwoMicWA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,247,1725346800"; d="scan'208";a="83566317" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Oct 2024 14:05:18 -0700 Date: Thu, 31 Oct 2024 23:05:50 +0200 From: Imre Deak To: Abel Vesa Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Karol Herbst , Lyude Paul , Danilo Krummrich , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Bjorn Andersson , Konrad Dybcio , Johan Hovold , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, nouveau@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Subject: Re: [PATCH RFC 1/4] drm/dp: Add helper to set LTTPRs in transparent mode Message-ID: Reply-To: imre.deak@intel.com References: <20241031-drm-dp-msm-add-lttpr-transparent-mode-set-v1-0-cafbb9855f40@linaro.org> <20241031-drm-dp-msm-add-lttpr-transparent-mode-set-v1-1-cafbb9855f40@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241031-drm-dp-msm-add-lttpr-transparent-mode-set-v1-1-cafbb9855f40@linaro.org> On Thu, Oct 31, 2024 at 05:12:45PM +0200, Abel Vesa wrote: > According to the DisplayPort standard, LTTPRs have two operating > modes: > - non-transparent - it replies to DPCD LTTPR field specific AUX > requests, while passes through all other AUX requests > - transparent - it passes through all AUX requests. > > Switching between this two modes is done by the DPTX by issuing > an AUX write to the DPCD PHY_REPEATER_MODE register. > > Add a generic helper that allows switching between these modes. > > Signed-off-by: Abel Vesa > --- > drivers/gpu/drm/display/drm_dp_helper.c | 17 +++++++++++++++++ > include/drm/display/drm_dp_helper.h | 1 + > 2 files changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c > index 6ee51003de3ce616c3a52653c2f1979ad7658e21..38d612345986ad54b42228902ea718a089d169c4 100644 > --- a/drivers/gpu/drm/display/drm_dp_helper.c > +++ b/drivers/gpu/drm/display/drm_dp_helper.c > @@ -2694,6 +2694,23 @@ int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) > } > EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate); > > +/** > + * drm_dp_lttpr_set_transparent_mode - set the LTTPR in transparent mode > + * @aux: DisplayPort AUX channel > + * @enable: Enable or disable transparent mode > + * > + * Returns 0 on success or a negative error code on failure. Should be "Returns 1 on success". > + */ > + > +int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable) > +{ > + u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : > + DP_PHY_REPEATER_MODE_NON_TRANSPARENT; > + > + return drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_MODE, val); > +} > +EXPORT_SYMBOL(drm_dp_lttpr_set_transparent_mode); > + > /** > * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs > * @caps: LTTPR common capabilities > diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h > index 279624833ea9259809428162f4e845654359f8c9..8821ab2d36b0e04d38ccbdddcb703b34de7ed680 100644 > --- a/include/drm/display/drm_dp_helper.h > +++ b/include/drm/display/drm_dp_helper.h > @@ -625,6 +625,7 @@ int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, > u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); > int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); > +int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable); > int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); > bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); > > -- > 2.34.1 >