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charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: ZePCRRglmEQEOquWuhpfVvX4xvzF1IPW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMwMDA4NyBTYWx0ZWRfX/cr1QTg6OY7Q Oya2BZJxNeFby/bNE+wi5FFpHkY3Zi18uG4FECmTdRyltINc7VmOedWH3a9+8KOIJsSpOboP16b NKJiez9S3b4052iC8aI9pkjF/joElza+K+AwnMqA5HEWXm32VIvyPKKatwzlVT/Hq8b2v9MgDaN rlmxmr2+u5yeDcknFfH62HvvPiBir941ff5iQ5wMnSV+7Hlo+hHMwaPSLU9Lv0ME3EXJPV1MMvQ IwddzEmxUhXtCrmfxQ3Zfk25/Bb79UjqtsoTeqMb1zrGj4zn3yG/45ZrpPOx7s/9YoYczylSyQZ xSYoiiUqNq9Mug5Wk9FdigtMeIKKnP/aBdu20+kavj3s9BXBcWnUKie1WOLiEirjzadKr1EgvbP xm+kNjzaEc5pu9pAN281eC6FmcK8YQ== X-Authority-Analysis: v=2.4 cv=a/Q9NESF c=1 sm=1 tr=0 ts=690341a1 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Z2WFzCv5d8wuYGPiYnEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-ORIG-GUID: ZePCRRglmEQEOquWuhpfVvX4xvzF1IPW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-30_03,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 suspectscore=0 phishscore=0 spamscore=0 adultscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510300087 On 10/29/2025 4:06 PM, Dmitry Baryshkov wrote: > On Wed, Oct 29, 2025 at 03:30:54PM +0530, Taniya Das wrote: >> >> >> On 9/25/2025 3:46 PM, Konrad Dybcio wrote: >>>> + tcsrcc: clock-controller@1fd5044 { >>>> + compatible = "qcom,glymur-tcsr"; >>>> + reg = <0x0 0x1fd5044 0x0 0x48>; >>> We can map 0x1fd5000 - 0x1fd5094 inclusive, as that seems like a >>> logical subblock (this would require adjusting the driver) >>> >> >> Konrad, we encountered issues when trying to map regions beyond just the >> clock reference registers. Normally, we map the entire address range of >> a clock controller (CC) module in the device tree. However, for TCSRCC >> where CLKREF_EN registers are located within shared modules like TCSR or >> TLMM—we don't own the whole address space, and mapping the full range >> can overlap with other devices. >> To avoid this, we propose defining the base address as the first >> register actually used, and the size to only include up to the last >> register we use. This ensures we only map the relevant subblock, >> preventing conflicts with other device nodes. > > Then you need to behave slightly differently: map the full range at the > basic device (TLMM, TCSR, etc.) and then create TCSRCC as a child device > to that node (and use paren't regmap to access the registers). > Dmitry, I agree that this approach is ideal. However, the current hardware implementation isn’t consistent across multiple SoCs, which means the driver design also needs to adapt. Given these differences, we decided to strictly map only the range of hardware registers that are actually used for clocks, rather than the entire module. >> >> So want to keep the mapping same from the start of clockref clocks. >> >>> There's also a laaaarge pool of various TCSR_ registers between >>> the previous node and this one.. but we can leave that in case we >>> need to describe it in a specific way some day >>>> + #clock-cells = <1>; >>>> + #reset-cells = <1>; >>>> + }; >>>> + >> >> -- >> Thanks, >> Taniya Das >> > -- Thanks, Taniya Das