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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bbe6a64d4cbsm12589166b.16.2026.04.30.08.44.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Apr 2026 08:44:05 -0700 (PDT) Message-ID: Date: Thu, 30 Apr 2026 17:44:03 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 07/13] clk: qcom: clk-alpha-pll: Add support to skip PLL configuration To: Jagadeesh Kona , Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Neil Armstrong , Lee Jones , Ajit Pandey , Imran Shaik , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Maulik Shah , Taniya Das References: <20260420-cesta-sm870-dispcc-v1-0-eb27d845df9c@oss.qualcomm.com> <20260420-cesta-sm870-dispcc-v1-7-eb27d845df9c@oss.qualcomm.com> <5vkpjjuq6vh2mr4lcq5cwqd4h5cbserf3n756d465kheuwl5fk@tu3amjwe5k57> <269bdec3-6340-4b27-9b38-3fc1dfc958c8@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Ev/iaycA c=1 sm=1 tr=0 ts=69f378c7 cx=c_pps a=N1BjEkVkxJi3uNfLdpvX3g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=C5MmyifQ20IcwxlzDtwA:9 a=0bXxn9q0MV6snEgNplNhOjQmxlI=:19 a=QEXdDO2ut3YA:10 a=crWF4MFLhNY0qMRaF8an:22 X-Proofpoint-ORIG-GUID: xju089ZhavMgHpigKiiwEUsj3tKaxJ5u X-Proofpoint-GUID: xju089ZhavMgHpigKiiwEUsj3tKaxJ5u X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDMwMDE2MiBTYWx0ZWRfX33GlElddrj34 TR6aqPGn1F/Zlr16chYZTTZ8ePsl6LO9mCNlaWQ60PyTZIg50bRe6swvSneMFWvLHsYOk1e9kOC jwiTV2kBJT5DRl0WF0oExGvRhgutGfbqF58j6W/jBGJc8GUmSg7DfmJmZDe1eocZIFJAoG4Ngkg j7s2mqqUmDzUCC58igdE4/0tNxUGSBpGHwaWVHNuk+H1MlzmJyQxmJ22gt92P8jyFSG+Oesr06u YVd5dcXIkVdKpdZMxpNNTQVHzE49AEu97EqiOnUA8y7k7IWNC6UhJ9r5NQrF75av3m8RLqHUXBN t557F4F/1UotSPNBtz9En3yNxHJCmj1DMZRXPqWSl33R0xuL8XIDOC8Uf5d1AtdhymCnSfVWLex Wu82e0AUAcijDejucbc9WN4Ay06DRqXcUcFI8z2rp1sGkd4qXB883X5UB7QrTyhsEIl4VE3Wrv2 1bkfeFX2kMNrYEsY+1A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-30_04,2026-04-30_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 phishscore=0 spamscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604300162 On 4/28/26 7:22 PM, Jagadeesh Kona wrote: > > > On 4/23/2026 4:43 PM, Konrad Dybcio wrote: >> On 4/22/26 8:28 PM, Dmitry Baryshkov wrote: >>> On Mon, Apr 20, 2026 at 09:59:00PM +0530, Jagadeesh Kona wrote: >>>> Some PLLs are already configured as part of CRM(CESTA Resource >>>> manager) initialization. Add support to skip PLL reconfiguration >>>> for such PLLs that are already configured. >>>> >>>> Signed-off-by: Jagadeesh Kona >>>> --- >>>> drivers/clk/qcom/clk-alpha-pll.c | 8 +++++++- >>>> 1 file changed, 7 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c >>>> index 67fc97739d0d4c26aec0bac5d43d1b87d297bc6a..2f4ebf4d3884b92c981dbe0e67245704a88881ad 100644 >>>> --- a/drivers/clk/qcom/clk-alpha-pll.c >>>> +++ b/drivers/clk/qcom/clk-alpha-pll.c >>>> @@ -2332,7 +2332,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops); >>>> void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, >>>> const struct alpha_pll_config *config) >>>> { >>>> - u32 lval = config->l; >>>> + u32 lval = config->l, regval; >>>> >>>> /* >>>> * If the bootloader left the PLL enabled it's likely that there are >>>> @@ -2343,6 +2343,12 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma >>>> return; >>>> } >>>> >>>> + /* Return early if PLL is already configured */ >>>> + regmap_read(regmap, PLL_L_VAL(pll), ®val); >>>> + regval &= LUCID_EVO_PLL_L_VAL_MASK; >>>> + if (regval) >>>> + return; >>>> + >>> >>> Why is it being applied only to Lucid EVO PLLs? >> > > Thanks Dmitry and Konrad for your reviews. > > This is the function used to configure all Taycan PLLs, currently all the PLLs > configured during CESTA initialization belong to Taycan type only. I will recheck > if similar logic is required for any additional PLL types also. > > >> These clocks already have a an .is_enabled() callback, could that be >> treated as equivalent? >> > > We already have is_enabled check to avoid configuring PLL's that are already enabled. > There can be case where PLL is configured from bootloader but not enabled during bootup. > This check avoids re-configuring such PLLs that are already configured by bootloader but > not enabled. Okay, that was the missing piece. Is this a micro-optimization, or something highly necessary (for e.g. glitch-free display)? Konrad