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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id f9-20020a2e9509000000b002b32d4a59d5sm530954ljh.117.2023.06.12.11.30.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 12 Jun 2023 11:30:06 -0700 (PDT) Message-ID: Date: Mon, 12 Jun 2023 21:30:05 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 2/2] drm/msm/dsi: don't allow enabling 7nm VCO with unprogrammed rate Content-Language: en-GB To: Marijn Suijten Cc: Rob Clark , Sean Paul , Abhinav Kumar , Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Degdag Mohamed References: <20230612031616.3620134-1-dmitry.baryshkov@linaro.org> <20230612031616.3620134-2-dmitry.baryshkov@linaro.org> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 12/06/2023 12:21, Marijn Suijten wrote: > On 2023-06-12 11:15:53, Marijn Suijten wrote: >> On 2023-06-12 06:16:16, Dmitry Baryshkov wrote: >>> CCF can try enabling VCO before the rate has been programmed. This can >>> cause clock lockups and/or other boot issues. Program the VCO to the >>> minimal PLL rate if the read rate is 0 Hz. >>> >>> Reported-by: Degdag Mohamed >>> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") >>> Signed-off-by: Dmitry Baryshkov >> >> This unfortunately regresses my Xperia 5 (sofef01 panel driver that's >> on the lists) to now run at 30~33Hz instead of 60Hz. I can provide >> debugging and clk trees later, if needed. > > I'll also retest the Xperia 1 with this, which has a 4k DSC panel. > > Is this intended to get rid of: > > msm_dsi_phy ae94400.phy: [drm:dsi_pll_7nm_vco_prepare] *ERROR* DSI PLL(0) lock failed, status=0x00000000: -110 > PLL(0) lock failed > > ... at startup (and relevant rcg2 update_config failures, unbalanced > disables etc)? It locks after a couple tries but it's still > unnecessarily spammy. Yes. > > - Marijn > >> >> - Marijn >> >>> --- >>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 5 +++++ >>> 1 file changed, 5 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> index 3b1ed02f644d..6979d35eb7c3 100644 >>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c >>> @@ -395,11 +395,16 @@ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) >>> wmb(); /* Ensure that the reset is deasserted */ >>> } >>> >>> +static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw, >>> + unsigned long parent_rate); >>> static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw) >>> { >>> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw); >>> int rc; >>> >>> + if (dsi_pll_7nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0) >>> + dsi_pll_7nm_vco_set_rate(hw, pll_7nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE); >>> + >>> dsi_pll_enable_pll_bias(pll_7nm); >>> if (pll_7nm->slave) >>> dsi_pll_enable_pll_bias(pll_7nm->slave); >>> -- >>> 2.39.2 >>> -- With best wishes Dmitry