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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5acca9sm17735885e9.12.2025.04.18.03.54.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 03:54:24 -0700 (PDT) Date: Fri, 18 Apr 2025 12:54:22 +0200 From: Daniel Lezcano To: Anjelique Melendez Cc: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, srinivas.kandagatla@linaro.org, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Subject: Re: [PATCH v3 1/5 RESEND] thermal: qcom-spmi-temp-alarm: enable stage 2 shutdown when required Message-ID: References: <20250320202408.3940777-1-anjelique.melendez@oss.qualcomm.com> <20250320202408.3940777-2-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250320202408.3940777-2-anjelique.melendez@oss.qualcomm.com> On Thu, Mar 20, 2025 at 01:24:04PM -0700, Anjelique Melendez wrote: > From: David Collins > > Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature > stage 2 automatic PMIC partial shutdown to be enabled in order to > avoid repeated faults in the event of reaching over-temperature > stage 3. Modify the stage 2 shutdown control logic to ensure that > stage 2 shutdown is enabled on all affected PMICs. Read the > digital major and minor revision registers to identify these > PMICs. > > Signed-off-by: David Collins > Signed-off-by: Anjelique Melendez > --- > drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 32 +++++++++++++++++++-- > 1 file changed, 30 insertions(+), 2 deletions(-) > > diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c > index c2d59cbfaea9..b2077ff9fe73 100644 > --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c > +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c > @@ -1,6 +1,7 @@ > // SPDX-License-Identifier: GPL-2.0-only > /* > * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved. > + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. > */ > > #include > @@ -16,6 +17,7 @@ > > #include "../thermal_hwmon.h" > > +#define QPNP_TM_REG_DIG_MINOR 0x00 > #define QPNP_TM_REG_DIG_MAJOR 0x01 > #define QPNP_TM_REG_TYPE 0x04 > #define QPNP_TM_REG_SUBTYPE 0x05 > @@ -71,6 +73,7 @@ struct qpnp_tm_chip { > struct device *dev; > struct thermal_zone_device *tz_dev; > unsigned int subtype; > + unsigned int dig_revision; > long temp; > unsigned int thresh; > unsigned int stage; > @@ -78,6 +81,7 @@ struct qpnp_tm_chip { > /* protects .thresh, .stage and chip registers */ > struct mutex lock; > bool initialized; > + bool require_s2_shutdown; > > struct iio_channel *adc; > const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; > @@ -255,7 +259,7 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, > > skip: > reg |= chip->thresh; > - if (disable_s2_shutdown) > + if (disable_s2_shutdown && !chip->require_s2_shutdown) > reg |= SHUTDOWN_CTRL1_OVERRIDE_S2; > > return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg); > @@ -350,7 +354,7 @@ static int qpnp_tm_probe(struct platform_device *pdev) > { > struct qpnp_tm_chip *chip; > struct device_node *node; > - u8 type, subtype, dig_major; > + u8 type, subtype, dig_major, dig_minor; > u32 res; > int ret, irq; > > @@ -403,6 +407,30 @@ static int qpnp_tm_probe(struct platform_device *pdev) > return dev_err_probe(&pdev->dev, ret, > "could not read dig_major\n"); > > + ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor); > + if (ret < 0) { > + dev_err(&pdev->dev, "could not read dig_minor\n"); > + return ret; > + } > + > + chip->dig_revision = (dig_major << 8) | dig_minor; I would move this inside the block below. > + if (chip->subtype == QPNP_TM_SUBTYPE_GEN2) { > + /* > + * Check if stage 2 automatic partial shutdown must remain > + * enabled to avoid potential repeated faults upon reaching > + * over-temperature stage 3. > + */ > + switch (chip->dig_revision) { > + case 0x0001: > + case 0x0002: > + case 0x0100: > + case 0x0101: > + chip->require_s2_shutdown = true; > + break; > + } > + } And move this block after the test below > + > if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1 > && subtype != QPNP_TM_SUBTYPE_GEN2)) { > dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", > -- > 2.34.1 > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog