From: Vinod Koul <vkoul@kernel.org>
To: Wenbin Yao <wenbin.yao@oss.qualcomm.com>
Cc: "Kishon Vijay Abraham I" <kishon@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com,
qiang.yu@oss.qualcomm.com,
"Prudhvi Yarlagadda" <quic_pyarlaga@quicinc.com>
Subject: Re: [PATCH v3 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHY
Date: Mon, 1 Sep 2025 18:16:54 +0530 [thread overview]
Message-ID: <aLWVvuGrxL2OQRSd@vaman> (raw)
In-Reply-To: <20250825-glymur_pcie5-v3-1-5c1d1730c16f@oss.qualcomm.com>
On 25-08-25, 23:01, Wenbin Yao wrote:
> From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
>
> The fifth PCIe instance on Glymur has a Gen5 4-lane PHY. Document it as a
> separate compatible.
This does not apply for me, please rebase and send
--
~Vinod
next prev parent reply other threads:[~2025-09-01 12:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-26 6:01 [PATCH v3 0/4] PCI: qcom: Add support for Glymur PCIe Gen5x4 Wenbin Yao
2025-08-26 6:01 ` [PATCH v3 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHY Wenbin Yao
2025-09-01 12:46 ` Vinod Koul [this message]
2025-08-26 6:01 ` [PATCH v3 2/4] dt-bindings: PCI: qcom: Document the Glymur PCIe Controller Wenbin Yao
2025-08-26 6:01 ` [PATCH v3 3/4] phy: qcom-qmp: pcs: Add v8.50 register offsets Wenbin Yao
2025-08-26 6:01 ` [PATCH v3 4/4] phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY Wenbin Yao
2025-08-26 6:19 ` Manivannan Sadhasivam
2025-08-27 1:45 ` Dmitry Baryshkov
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