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Thu, 20 Nov 2025 02:10:35 -0800 (PST) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29b5b13e7e6sm21535785ad.40.2025.11.20.02.10.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Nov 2025 02:10:34 -0800 (PST) Date: Thu, 20 Nov 2025 15:40:30 +0530 From: Abhinaba Rakshit To: Bryan O'Donoghue Cc: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org Subject: Re: [PATCH 1/2] soc: qcom: ice: enable ICE clock scaling API Message-ID: References: <20251001-enable-ufs-ice-clock-scaling-v1-0-ec956160b696@oss.qualcomm.com> <6PNEPfyjHahJ_pLSaxMINWXDHyO3NKVQD8Bo6XXlA7yI8Qcgim3MDd4gFC8LIMYAIFoAIHnttsDVc6LFEdBWCg==@protonmail.internalid> <20251001-enable-ufs-ice-clock-scaling-v1-1-ec956160b696@oss.qualcomm.com> <22a6cebc-bd09-48f5-a11e-ab925011bd8f@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <22a6cebc-bd09-48f5-a11e-ab925011bd8f@kernel.org> X-Authority-Analysis: v=2.4 cv=F59at6hN c=1 sm=1 tr=0 ts=691ee91c cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=kj9zAlcOel0A:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=k58wtyJiP0ZlwjBnw7gA:9 a=CjuIK1q_8ugA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: QNPSn3cYzid4LdT1j7JsVOJxT2G0sfms X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTIwMDA2MSBTYWx0ZWRfX9iH6EqL8H//P MZfZ4YRQduE6dggRvxqTbvwE76WsutfmlOX63NBW8JURd9PrqMKdKM+wL4KOaudBeszqzI4vjMB puSenEIbb1VIV2l+ywBOjS21c3TQApNpFB6wXEx7cn3ZLLKu0had0xbjTlJKyR4zsNM3LRIqZlg 8ZWzMr9XCNModTpwhU2iP/cR3U31lZD3Cw5uQFrO+ypq4weOMGDnDNqwCcty4Lnp8pn2RwHYMv+ /HUp4vDsFY5KtrzwofNNhhNIjn1cdyPryUh/EvkEdk6G+Iq4Pgu8xJVvfxXotoUExXhRgsCqxiY yF1Oxs8TboW+MaK+28CDetwS0cOz4AMVufiwdeVjaPibjxx4MseemcL6vbOCoi8RzfIp5UimBxj Dcrwfdcd4+pOmvTH8OtppJq4JpVl4w== X-Proofpoint-ORIG-GUID: QNPSn3cYzid4LdT1j7JsVOJxT2G0sfms X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-20_03,2025-11-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 impostorscore=0 phishscore=0 spamscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511200061 On Thu, Oct 02, 2025 at 01:21:22AM +0100, Bryan O'Donoghue wrote: > On 01/10/2025 12:38, Abhinaba Rakshit wrote: > > Add ICE clock scaling API based on the parsed clk supported > > frequencies from dt entry. > > > > Signed-off-by: Abhinaba Rakshit > > --- > > drivers/soc/qcom/ice.c | 25 +++++++++++++++++++++++++ > > include/soc/qcom/ice.h | 1 + > > 2 files changed, 26 insertions(+) > > > > diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c > > index c467b55b41744ebec0680f5112cc4bb1ba00c513..ec8d6bb9f426deee1038616282176bfc8e5b9ec1 100644 > > --- a/drivers/soc/qcom/ice.c > > +++ b/drivers/soc/qcom/ice.c > > @@ -97,6 +97,8 @@ struct qcom_ice { > > struct clk *core_clk; > > bool use_hwkm; > > bool hwkm_init_complete; > > + u32 max_freq; > > + u32 min_freq; > > }; > > > > static bool qcom_ice_check_supported(struct qcom_ice *ice) > > @@ -514,10 +516,25 @@ int qcom_ice_import_key(struct qcom_ice *ice, > > } > > EXPORT_SYMBOL_GPL(qcom_ice_import_key); > > > > +int qcom_ice_scale_clk(struct qcom_ice *ice, bool scale_up) > > +{ > > + int ret = 0; > > + > > + if (scale_up && ice->max_freq) > > + ret = clk_set_rate(ice->core_clk, ice->max_freq); > > + else if (!scale_up && ice->min_freq) > > + ret = clk_set_rate(ice->core_clk, ice->min_freq); > > + > > + return ret; > > +} > > +EXPORT_SYMBOL_GPL(qcom_ice_scale_clk); > > + > > static struct qcom_ice *qcom_ice_create(struct device *dev, > > void __iomem *base) > > { > > struct qcom_ice *engine; > > + const __be32 *prop; > > + int len; > > > > if (!qcom_scm_is_available()) > > return ERR_PTR(-EPROBE_DEFER); > > @@ -549,6 +566,14 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, > > if (IS_ERR(engine->core_clk)) > > return ERR_CAST(engine->core_clk); > > > > + prop = of_get_property(dev->of_node, "freq-table-hz", &len); > > + if (!prop || len < 2 * sizeof(uint32_t)) { > > + dev_err(dev, "Freq-hz property not found or invalid length\n"); > > If this error really happened you should pus the result code up the call > stack also since either case can be an error you can inform the user of > which error happened in your output string. Okay. However, we will move to using OPP table and hence, this logic might change. > > > + } else { > > + engine->min_freq = be32_to_cpu(prop[0]); > > + engine->max_freq = be32_to_cpu(prop[1]); > > You check for zero later on in the code but, is zero a valid value to be > returned here ? > > e.g. is it valid to specify "freq-table-hz" in your DT but then set max to > zero ? min to zero ? > > If not you may as well reject zero and dispense with the checks later on. Yes, zero is valid here (means "no scaling"), will document it in patchset v2. > > > + } > > + > > if (!qcom_ice_check_supported(engine)) > > return ERR_PTR(-EOPNOTSUPP); > > > > diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h > > index 4bee553f0a59d86ec6ce20f7c7b4bce28a706415..b701ec9e062f70152f6dea8bf6c4637ab6ef20f1 100644 > > --- a/include/soc/qcom/ice.h > > +++ b/include/soc/qcom/ice.h > > @@ -30,5 +30,6 @@ int qcom_ice_import_key(struct qcom_ice *ice, > > const u8 *raw_key, size_t raw_key_size, > > u8 lt_key[BLK_CRYPTO_MAX_HW_WRAPPED_KEY_SIZE]); > > struct qcom_ice *devm_of_qcom_ice_get(struct device *dev); > > +int qcom_ice_scale_clk(struct qcom_ice *ice, bool scale_up); > > > > #endif /* __QCOM_ICE_H__ */ > > > > -- > > 2.34.1 > > > > >