From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from m-r2.th.seeweb.it (m-r2.th.seeweb.it [5.144.164.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C722D3A1D2 for ; Wed, 24 Dec 2025 17:43:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.144.164.171 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766598221; cv=none; b=qDDbhmvw7FANBuVYcokfMxOH3spSTBzqu4zUZ02y1wwgW1DmnG7Zv+9aRXXQeceXL7zSlKfvyClFQjQ/uVk42U/wy1qxW/YKW4TIGQ2b6j07/H1V/frPHXr9JqxI5X3DwPcy1XBMbCSjMeBIi6M1EpgONOHP8WZzin+AEWP53Fs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766598221; c=relaxed/simple; bh=aiIbeqaSWhXacD5KcP9eKQ3ow9f9uZ3BjS6V2DVhCHs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=DChsdXyVfhxPDo9pmaw9ycUmP/HyRX9H7Q0CORr9ras0UcJOYy4WH4gmkjQhHTRaveVvofJGgtZoYc0Zq1mKm5J62r4dro3rmij70eMh4Y44OIuWNISUVAY6HYWvV/+ue3wD2YSNXcPmC/1ZqhCSFZZC+hS07THiKulGw5DevXc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=somainline.org; spf=pass smtp.mailfrom=somainline.org; arc=none smtp.client-ip=5.144.164.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=somainline.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=somainline.org Received: from SoMainline.org (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 9F19F3F43C; Wed, 24 Dec 2025 18:27:00 +0100 (CET) Date: Wed, 24 Dec 2025 18:26:59 +0100 From: Marijn Suijten To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , David Airlie , Simona Vetter , Teguh Sobirin , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 1/2] drm/msm/dpu: Set vsync source irrespective of mdp top support Message-ID: References: <20251224-intf-fix-wd-v4-0-07a0926fafd2@oss.qualcomm.com> <20251224-intf-fix-wd-v4-1-07a0926fafd2@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251224-intf-fix-wd-v4-1-07a0926fafd2@oss.qualcomm.com> On 2025-12-24 17:33:49, Dmitry Baryshkov wrote: > From: Teguh Sobirin > > Since DPU 5.x the vsync source TE setup is split between MDP TOP and > INTF blocks. Currently all code to setup vsync_source is only exectued exectued -> executed typo remains since v2. > if MDP TOP implements the setup_vsync_source() callback. However on Double space to match the above, on two occasions: ^^ > DPU >= 8.x this callback is not implemented, making DPU driver skip all > vsync setup. Move the INTF part out of this condition, letting DPU ^^ double space too > driver to setup TE vsync selection on all new DPU devices. > > Signed-off-by: Teguh Sobirin > Fixes: 2f69e5458447 ("drm/msm/dpu: skip watchdog timer programming through TOP on >= SM8450") > [DB: restored top->ops.setup_vsync_source call] > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 17 +++++++++-------- > 1 file changed, 9 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index d1cfe81a3373..0482b2bb5a9e 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -774,6 +774,9 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, > return; > } > > + /* Set vsync source irrespective of mdp top support */ I still think this comment is redundant, as mentioned in v2. Regardless: Reviewed-by: Marijn Suijten > + vsync_cfg.vsync_source = disp_info->vsync_source; > + > if (hw_mdptop->ops.setup_vsync_source) { > for (i = 0; i < dpu_enc->num_phys_encs; i++) > vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx; > @@ -781,17 +784,15 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, > vsync_cfg.pp_count = dpu_enc->num_phys_encs; > vsync_cfg.frame_rate = drm_mode_vrefresh(&dpu_enc->base.crtc->state->adjusted_mode); > > - vsync_cfg.vsync_source = disp_info->vsync_source; > - > hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg); > + } > > - for (i = 0; i < dpu_enc->num_phys_encs; i++) { > - phys_enc = dpu_enc->phys_encs[i]; > + for (i = 0; i < dpu_enc->num_phys_encs; i++) { > + phys_enc = dpu_enc->phys_encs[i]; > > - if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) > - phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, > - vsync_cfg.vsync_source); > - } > + if (phys_enc->has_intf_te && phys_enc->hw_intf->ops.vsync_sel) > + phys_enc->hw_intf->ops.vsync_sel(phys_enc->hw_intf, > + vsync_cfg.vsync_source); > } > } > > > -- > 2.47.3 >