From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70B1440FD83; Tue, 20 Jan 2026 14:49:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768920565; cv=none; b=MP6oN6DGlWSaHDfX6Yy+jqnJ/1+YiEJjV9WvUBeK8LXI7K9xtXC4px2T+f+xp+amk6Wu3UNI2uQ5IWh0k4TZzw5m8NOqPXp8X609l35yvXmDCSZMkgTubIhvxkxWzgbOfZ8dTBC0F++772iMD43GX8EaknCZw2LM6ULiyk1PcIQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768920565; c=relaxed/simple; bh=nULy7iP1bl6qjT9VFD0rfE4QULF0hzfHdm7VN2KfVMg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=BwwRBOsky5KicARzwnhvXpyY9a1nGYBi/TX7+q+SahzbgEo6q5yaNSEuFiwvliwmvJopZYgsE1vNKXOyM2uwYXKXOXKkga4ObS5k77P/UVJf/ZPMF3NS/dMbJUbpS6gMNppTSeuYEITPi6Y26J/aNiXYe18rf1MQshxykcjLh2w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=KFT8aE1L; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="KFT8aE1L" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768920563; x=1800456563; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=nULy7iP1bl6qjT9VFD0rfE4QULF0hzfHdm7VN2KfVMg=; b=KFT8aE1Le3Dpf/5rQNV0fhl/h22E/jipDf+Rknu0aY/VMskWehSrKezG qvi96kvSqkK3/2cjY4lSJ1hIGfqGJDleN4/Yc8y/AVSRy85QUz9Pbg8Uj R5pAebsjtIQLtux6bzuPYbbj/KKkxa0xyYxgHr3k6boZ8mzJsP/cTg+FS IrOXeER60CR921F5la7Mva3hGo0SELDLsAYL4zfTrTuG9sByW4ilagX/i 9Qlxp6LiNDR3XOESXKAcVPUu5JAhJm6ZHJrohZKeIA/NpH+GHIqDtaBG/ CL3Q9/9wmiA4McZlVe+rto2PImKPpHOnIHenxyys0CchgCT2XXWoRatOI Q==; X-CSE-ConnectionGUID: V8orAiS6Tv2YHBaLvr4+rQ== X-CSE-MsgGUID: sU4TfuPJQyOgPgVYsXnlOg== X-IronPort-AV: E=McAfee;i="6800,10657,11677"; a="70102250" X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="70102250" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2026 06:49:23 -0800 X-CSE-ConnectionGUID: LewO+RjgT0WgtrthwjMNIg== X-CSE-MsgGUID: Cmu3ZY1WSJCS6EYI+guxAA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="211142150" Received: from fpallare-mobl4.ger.corp.intel.com (HELO kekkonen.fi.intel.com) ([10.245.244.188]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jan 2026 06:49:19 -0800 Received: from kekkonen.localdomain (localhost [IPv6:::1]) by kekkonen.fi.intel.com (Postfix) with SMTP id D62C511F82F; Tue, 20 Jan 2026 16:49:21 +0200 (EET) Date: Tue, 20 Jan 2026 16:49:21 +0200 Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo From: Sakari Ailus To: Bryan O'Donoghue Cc: Richard Acayan , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Tianshu Qiu , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Robert Mader , Vladimir Zapolskiy , David Heidelberg , phone-devel@vger.kernel.org Subject: Re: [PATCH v7 2/5] media: i2c: imx355: Support devicetree and power management Message-ID: References: <20260117040657.27043-1-mailingradian@gmail.com> <20260117040657.27043-3-mailingradian@gmail.com> <578668b0-cba2-4550-b676-26ed0b447bf2@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <578668b0-cba2-4550-b676-26ed0b447bf2@linaro.org> Hi Bryan, others, On Tue, Jan 20, 2026 at 12:44:24PM +0000, Bryan O'Donoghue wrote: > I think reset should be asserted before regulators and power are switched > on. i.e. before you try to switch the chip on, you should establish that the > reset pin is in the state that the timing diagram calls for. Indeed. The xshutdown pin, as it is typically called labelled as "reset" in this case, functions as both hardware reset and hardware standby mode control. It should be asserted (i.e. be set to low level) whenever the sensor is expected to be powered off. Typically deasserting it is the last step in the sensor's power-up sequence. This applies to nearly all CSI-2 and DVP (parallel) camera sensors. (There are some exceptions that use explicitly two GPIOs for similar functions but there are very few of them.) -- Regards, Sakari Ailus