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Wed, 13 Nov 2024 14:06:41 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4ADE6eRi015303 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Nov 2024 14:06:40 GMT Received: from [10.217.217.28] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 13 Nov 2024 06:06:32 -0800 Message-ID: Date: Wed, 13 Nov 2024 19:36:29 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V4 3/4] iio: adc: Add support for QCOM PMIC5 Gen3 ADC To: Krzysztof Kozlowski , , , , , , , , , , , , , , , CC: , , , , , , , , , , , , References: <20241030185854.4015348-1-quic_jprakash@quicinc.com> <20241030185854.4015348-4-quic_jprakash@quicinc.com> Content-Language: en-US From: Jishnu Prakash In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: sygkL2jZDiEXDNkAJWesywvqBVYpHxIb X-Proofpoint-GUID: sygkL2jZDiEXDNkAJWesywvqBVYpHxIb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 adultscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 malwarescore=0 spamscore=0 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411130120 Hi Krzysztof, On 10/31/2024 4:33 PM, Krzysztof Kozlowski wrote: > On 30/10/2024 19:58, Jishnu Prakash wrote: >> + >> +static int adc5_gen3_read(struct adc5_device_data *adc, unsigned int sdam_index, >> + u16 offset, u8 *data, int len) >> +{ >> + return regmap_bulk_read(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len); >> +} >> + >> +static int adc5_gen3_write(struct adc5_device_data *adc, unsigned int sdam_index, >> + u16 offset, u8 *data, int len) >> +{ >> + return regmap_bulk_write(adc->regmap, adc->base[sdam_index].base_addr + offset, data, len); >> +} >> + >> +/* >> + * Worst case delay from PBS in readying handshake bit >> + * can be up to 15ms, when PBS is busy running other >> + * simultaneous transactions, while in the best case, it is >> + * already ready at this point. Assigning polling delay and >> + * retry count accordingly. >> + */ >> + >> +#define ADC5_GEN3_HS_DELAY_MIN_US 100 >> +#define ADC5_GEN3_HS_DELAY_MAX_US 110 >> +#define ADC5_GEN3_HS_RETRY_COUNT 150 >> + >> +static int adc5_gen3_poll_wait_hs(struct adc5_device_data *adc, >> + unsigned int sdam_index) >> +{ >> + u8 conv_req = ADC5_GEN3_CONV_REQ_REQ; >> + int ret, count; >> + u8 status = 0; >> + >> + for (count = 0; count < ADC5_GEN3_HS_RETRY_COUNT; count++) { >> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_HS, &status, 1); >> + if (ret) >> + return ret; >> + >> + if (status == ADC5_GEN3_HS_READY) { >> + ret = adc5_gen3_read(adc, sdam_index, ADC5_GEN3_CONV_REQ, >> + &conv_req, 1); >> + if (ret) >> + return ret; >> + >> + if (!conv_req) >> + return 0; >> + } >> + >> + usleep_range(ADC5_GEN3_HS_DELAY_MIN_US, ADC5_GEN3_HS_DELAY_MAX_US); >> + } >> + >> + pr_err("Setting HS ready bit timed out, sdam_index:%d, status:%#x\n", sdam_index, status); >> + return -ETIMEDOUT; >> +} >> + >> +static void adc5_gen3_update_dig_param(struct adc5_channel_common_prop *prop, u8 *data) >> +{ >> + /* Update calibration select and decimation ratio select */ >> + *data &= ~(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK | ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK); >> + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_CAL_SEL_MASK, prop->cal_method); >> + *data |= FIELD_PREP(ADC5_GEN3_DIG_PARAM_DEC_RATIO_SEL_MASK, prop->decimation); >> +} >> + >> +static int adc5_gen3_status_clear(struct adc5_device_data *adc, >> + int sdam_index, u16 offset, u8 *val, int len) >> +{ > > Wait, what? Why are you defining functions in header causing multiple > copies of them? And even if: why this is not inline? But regardless: > this is a strong NAK from me. This was meant to hold macros and some helper functions used in both main and auxiliary driver files. I see what you mean - I'll move the function definitions into a new .c file and mark them inline. Thanks, Jishnu > > Best regards, > Krzysztof >