Re: [PATCH v2] soc: qcom: ubwc: disable bank swizzling for Glymur platform

[Bjorn Andersson <andersson@kernel.org>]

On Mon, Mar 16, 2026 at 04:51:46AM +0200, Dmitry Baryshkov wrote:
> On Sun, Mar 15, 2026 at 08:41:02PM -0500, Bjorn Andersson wrote:
> > On Fri, Mar 06, 2026 at 05:15:32PM +0200, Dmitry Baryshkov wrote:
> > > On Sat, Feb 28, 2026 at 08:34:27PM +0200, Dmitry Baryshkov wrote:
> > > > Due to the way the DDR controller is organized on Glymur, hardware
> > > > engineers strongly recommended disabling UBWC bank swizzling on Glymur.
> > > > Follow that recommendation.
> > > > 
> > > > Fixes: 9b21c3bd2480 ("soc: qcom: ubwc: Add configuration Glymur platform")
> > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > > > ---
> > > > Changes in v2:
> > > > - Fix the syntax error...
> > > > - Link to v1: https://lore.kernel.org/r/20260228-fix-glymur-ubwc-v1-1-d80e3fe0dcc7@oss.qualcomm.com
> > > > ---
> > > >  drivers/soc/qcom/ubwc_config.c | 3 +--
> > > >  1 file changed, 1 insertion(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
> > > > index 1c25aaf55e52..8304463f238a 100644
> > > > --- a/drivers/soc/qcom/ubwc_config.c
> > > > +++ b/drivers/soc/qcom/ubwc_config.c
> > > > @@ -231,8 +231,7 @@ static const struct qcom_ubwc_cfg_data x1e80100_data = {
> > > >  static const struct qcom_ubwc_cfg_data glymur_data = {
> > > >  	.ubwc_enc_version = UBWC_5_0,
> > > >  	.ubwc_dec_version = UBWC_5_0,
> > > > -	.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
> > > > -			UBWC_SWIZZLE_ENABLE_LVL3,
> > > > +	.ubwc_swizzle = 0,
> > > >  	.ubwc_bank_spread = true,
> > > >  	/* TODO: highest_bank_bit = 15 for LP_DDR4 */
> > > >  	.highest_bank_bit = 16,
> > > 
> > > Carrying over from v1 discussion.
> > > 
> > > Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> > > 
> > > It depends on the fix which is currently a part of msm-fixes for the
> > > device to function correctly. Raised the question on IRC regarding the
> > > immutable tag or any other proper way to merge it.
> > > 
> > 
> > Sorry, I did see your question on IRC, but didn't follow up and forgot
> > to ask about it.
> > 
> > What do you mean with "depends on"? Why do we need an immutable tag?
> 
> Disabling LVL2 / LVL3 swizzling on the GPU side requires the patch from
> msm-fixes. Otherwise the GPU driver ignores passed swizzle, making the
> hardware use incorrect memory layout in case of Glymur (A8xx).
> 

So this patch must appear after the change in msm-fixes?

If you have already gotten the msm-fixes merged upstream, in which case
ordering is already achieved, without the immutable branch... 
If you haven't, the immutable branch is not going to help, as it doesn't
guarantee that the immutable changes arrives in torvalds/master only
after the msm-fixes.

That said, this seems somewhat theoretical, as there's no GPU enabled in
the upstream DTSI afaict.

Regards,
Bjorn

> -- 
> With best wishes
> Dmitry