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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id a13-20020ac2520d000000b004edc72be17csm522583lfl.2.2023.04.18.05.16.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Apr 2023 05:16:53 -0700 (PDT) Message-ID: Date: Tue, 18 Apr 2023 14:16:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v2 03/17] drm/msm/dpu: Move non-MDP_TOP INTF_INTR offsets out of hwio header Content-Language: en-US To: Marijn Suijten , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Adam Skladowski , Loic Poulain , Bjorn Andersson , Kuogee Hsieh , Robert Foss , Vinod Koul , Rajesh Yadav , Jeykumar Sankaran , Neil Armstrong , Chandan Uddaraju Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Martin Botka , Jami Kettunen , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jordan Crouse , Archit Taneja , Sravanthi Kollukuduru References: <20230411-dpu-intf-te-v2-0-ef76c877eb97@somainline.org> <20230411-dpu-intf-te-v2-3-ef76c877eb97@somainline.org> From: Konrad Dybcio In-Reply-To: <20230411-dpu-intf-te-v2-3-ef76c877eb97@somainline.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 17.04.2023 22:21, Marijn Suijten wrote: > These offsets do not fall under the MDP TOP block and do not fit the > comment right above. Move them to dpu_hw_interrupts.c next to the > repsective MDP_INTF_x_OFF interrupt block offsets. > > Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") > Signed-off-by: Marijn Suijten > --- Reviewed-by: Konrad Dybcio Konrad > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 5 ++++- > drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h | 3 --- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > index 53326f25e40e..85c0bda3ff90 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > @@ -15,7 +15,7 @@ > > /* > * Register offsets in MDSS register file for the interrupt registers > - * w.r.t. to the MDP base > + * w.r.t. the MDP base > */ > #define MDP_SSPP_TOP0_OFF 0x0 > #define MDP_INTF_0_OFF 0x6A000 > @@ -24,6 +24,9 @@ > #define MDP_INTF_3_OFF 0x6B800 > #define MDP_INTF_4_OFF 0x6C000 > #define MDP_INTF_5_OFF 0x6C800 > +#define INTF_INTR_EN 0x1c0 > +#define INTF_INTR_STATUS 0x1c4 > +#define INTF_INTR_CLEAR 0x1c8 > #define MDP_AD4_0_OFF 0x7C000 > #define MDP_AD4_1_OFF 0x7D000 > #define MDP_AD4_INTR_EN_OFF 0x41c > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h > index feb9a729844a..5acd5683d25a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h > @@ -21,9 +21,6 @@ > #define HIST_INTR_EN 0x01c > #define HIST_INTR_STATUS 0x020 > #define HIST_INTR_CLEAR 0x024 > -#define INTF_INTR_EN 0x1C0 > -#define INTF_INTR_STATUS 0x1C4 > -#define INTF_INTR_CLEAR 0x1C8 > #define SPLIT_DISPLAY_EN 0x2F4 > #define SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x2F8 > #define DSPP_IGC_COLOR0_RAM_LUTN 0x300 >