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[83.9.30.37]) by smtp.gmail.com with ESMTPSA id s5-20020a170906c30500b008552bc8399dsm14086113ejz.172.2023.01.20.05.16.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 20 Jan 2023 05:16:07 -0800 (PST) Message-ID: Date: Fri, 20 Jan 2023 14:16:05 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 3/4] arm64: dts: qcom: sm6350: Add CCI nodes Content-Language: en-US To: Luca Weiss , Andy Gross , Bjorn Andersson , Loic Poulain , Robert Foss , Rob Herring , Krzysztof Kozlowski Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221213-sm6350-cci-v2-0-15c2c14c34bb@fairphone.com> <20221213-sm6350-cci-v2-3-15c2c14c34bb@fairphone.com> From: Konrad Dybcio In-Reply-To: <20221213-sm6350-cci-v2-3-15c2c14c34bb@fairphone.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 20.01.2023 14:13, Luca Weiss wrote: > Add nodes for the two CCI blocks found on SM6350. > > The first contains two i2c busses and while the second one might also > contains two busses, the downstream kernel only has one configured, and > some boards use the GPIOs for the potential cci1_i2c1 one other > purposes, so leave that one unconfigured. > > Signed-off-by: Luca Weiss > --- Reviewed-by: Konrad Dybcio Konrad > arch/arm64/boot/dts/qcom/sm6350.dtsi | 132 +++++++++++++++++++++++++++++++++++ > 1 file changed, 132 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index 300ced5cda57..802d7f494162 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -6,6 +6,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -1435,6 +1436,95 @@ usb_1_dwc3: usb@a600000 { > }; > }; > > + cci0: cci@ac4a000 { > + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; > + reg = <0 0x0ac4a000 0 0x1000>; > + interrupts = ; > + power-domains = <&camcc TITAN_TOP_GDSC>; > + > + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, > + <&camcc CAMCC_SOC_AHB_CLK>, > + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, > + <&camcc CAMCC_CPAS_AHB_CLK>, > + <&camcc CAMCC_CCI_0_CLK>, > + <&camcc CAMCC_CCI_0_CLK_SRC>; > + clock-names = "camnoc_axi", > + "soc_ahb", > + "slow_ahb_src", > + "cpas_ahb", > + "cci", > + "cci_src"; > + > + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, > + <&camcc CAMCC_CCI_0_CLK>; > + assigned-clock-rates = <80000000>, <37500000>; > + > + pinctrl-0 = <&cci0_default &cci1_default>; > + pinctrl-1 = <&cci0_sleep &cci1_sleep>; > + pinctrl-names = "default", "sleep"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + cci0_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci0_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + cci1: cci@ac4b000 { > + compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; > + reg = <0 0x0ac4b000 0 0x1000>; > + interrupts = ; > + power-domains = <&camcc TITAN_TOP_GDSC>; > + > + clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, > + <&camcc CAMCC_SOC_AHB_CLK>, > + <&camcc CAMCC_SLOW_AHB_CLK_SRC>, > + <&camcc CAMCC_CPAS_AHB_CLK>, > + <&camcc CAMCC_CCI_1_CLK>, > + <&camcc CAMCC_CCI_1_CLK_SRC>; > + clock-names = "camnoc_axi", > + "soc_ahb", > + "slow_ahb_src", > + "cpas_ahb", > + "cci", > + "cci_src"; > + > + assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, > + <&camcc CAMCC_CCI_1_CLK>; > + assigned-clock-rates = <80000000>, <37500000>; > + > + pinctrl-0 = <&cci2_default>; > + pinctrl-1 = <&cci2_sleep>; > + pinctrl-names = "default", "sleep"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + cci1_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ > + }; > + > camcc: clock-controller@ad00000 { > compatible = "qcom,sm6350-camcc"; > reg = <0 0x0ad00000 0 0x16000>; > @@ -1522,6 +1612,48 @@ tlmm: pinctrl@f100000 { > #interrupt-cells = <2>; > gpio-ranges = <&tlmm 0 0 157>; > > + cci0_default: cci0-default-state { > + pins = "gpio39", "gpio40"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + cci0_sleep: cci0-sleep-state { > + pins = "gpio39", "gpio40"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + cci1_default: cci1-default-state { > + pins = "gpio41", "gpio42"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + cci1_sleep: cci1-sleep-state { > + pins = "gpio41", "gpio42"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + cci2_default: cci2-default-state { > + pins = "gpio43", "gpio44"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + cci2_sleep: cci2-sleep-state { > + pins = "gpio43", "gpio44"; > + function = "cci_i2c"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > sdc2_off_state: sdc2-off-state { > clk-pins { > pins = "sdc2_clk"; >