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Mon, 23 Mar 2026 10:12:42 -0700 (PDT) X-Received: by 2002:a17:90b:1a91:b0:35b:929f:7e95 with SMTP id 98e67ed59e1d1-35bd2c20675mr10918187a91.4.1774285961848; Mon, 23 Mar 2026 10:12:41 -0700 (PDT) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35bd3d8c462sm10077241a91.0.2026.03.23.10.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Mar 2026 10:12:41 -0700 (PDT) Date: Mon, 23 Mar 2026 22:42:34 +0530 From: Abhinaba Rakshit To: Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Neeraj Soni Cc: linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Konrad Dybcio Subject: Re: [PATCH v7 3/3] soc: qcom: ice: Set ICE clk to TURBO on probe Message-ID: References: <20260302-enable-ufs-ice-clock-scaling-v7-0-669b96ecadd8@oss.qualcomm.com> <20260302-enable-ufs-ice-clock-scaling-v7-3-669b96ecadd8@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260302-enable-ufs-ice-clock-scaling-v7-3-669b96ecadd8@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=GIIF0+NK c=1 sm=1 tr=0 ts=69c1748b cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=i-sMpDq2_rzAXM5hadQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzIzMDEyNyBTYWx0ZWRfX/8jRvMay07jF xYP6G90OIZ/MDC/so0BU52HIlkTVRwWKPB0gwDhbTnyuH1Ix1eANEDk7kpGVJeL8WGo/yR2Cofc aewpqpc3HLgI6h3Vf4UXdBfU2jQ0fAtKPWAJbHORrdrui8ebJa/D/sjcKg7+HIFyJD6/gsoKZRu MkjEIfLuYB+g3Q0Ljq8zqK7F1/obsuO4sWMEZauIvr1Vl0WDQZyACnl3+/iL/Osr1V8f6uan7gH x58vj5sQxjgB4+0q7ICL3qJ7pyzccHutlUlE6wKZnTzecAQFxYpEF72DTbq9X6HLqCil0RBXVyQ 1nUgWf79mh388lt6VHkC0lt+WjUBRI4I/iVgSrHPQfT/aXomgrfkz7/XM5jSMZ6gBFWXd9nErGJ DoD2N4K5BO0gQTo6C18++EBhYJKwrLw+SZ9pzqrefwqq4kTxq+gV+n29k8Of0LBp1N2K3W1F7zs BzwHVT1gpeE2cz6WxoA== X-Proofpoint-GUID: B2UJNK9hzMPVX9Qy0o_zf5pfSdlVl2UM X-Proofpoint-ORIG-GUID: B2UJNK9hzMPVX9Qy0o_zf5pfSdlVl2UM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-23_04,2026-03-23_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 malwarescore=0 priorityscore=1501 phishscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603230127 On Mon, Mar 02, 2026 at 04:19:15PM +0530, Abhinaba Rakshit wrote: > MMC controller lacks a clock scaling mechanism, unlike the UFS > controller. By default, the MMC controller is set to TURBO mode > during probe, but the ICE clock remains at XO frequency, > leading to read/write performance degradation on eMMC. > > To address this, set the ICE clock to TURBO during probe to > align it with the controller clock. This ensures consistent > performance and avoids mismatches between the controller > and ICE clock frequencies. > > For platforms where ICE is represented as a separate device, > use the OPP framework to vote for TURBO mode, maintaining > proper voltage and power domain constraints. > > Reviewed-by: Konrad Dybcio > Signed-off-by: Abhinaba Rakshit > --- > drivers/soc/qcom/ice.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c > index 7976a18d9a4cda1ad6b62b66ce011e244d0f6856..e8ee02a709574afa4ebb8e4395a8d899bf1d4976 100644 > --- a/drivers/soc/qcom/ice.c > +++ b/drivers/soc/qcom/ice.c > @@ -659,6 +659,13 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, > dev_info(dev, "ICE OPP table is not registered, please update your DT\n"); > } > > + if (engine->has_opp) { > + /* Vote for maximum clock rate for maximum performance */ > + err = dev_pm_opp_set_rate(dev, INT_MAX); > + if (err) > + dev_warn(dev, "Failed boosting the ICE clk to TURBO\n"); > + } > + > engine->core_clk_freq = clk_get_rate(engine->core_clk); > if (!qcom_ice_check_supported(engine)) > return ERR_PTR(-EOPNOTSUPP); Hi Konrad Since you previously reviewed this change, I wanted to share an improved approach that I recently realized for handling ICE clock scaling in the MMC use‑case. So far, we have been voting for the maximum frequency during the ICE device probe to align with MMC requirements. But because the ICE probe is common across different storage clients, applying the MAX vote at probe time may unintentionally impact other storage paths. Now that we have a generic scaling API exposed, we can make this logic MMC‑specific instead. In particular, within sdhci_msm_ice_init(). https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/mmc/host/sdhci-msm.c#n1966, we can invoke: qcom_ice_scale_clk(ice, INT_MAX, false); This ensures the MAX clock vote is applied only in the MMC context, without altering behavior for other storage clients relying on the ICE driver. I believe this results in a cleaner and correctly scoped design. Let me know your thoughts. Abhinaba Rakshit