From: Shawn Guo <shengchao.guo@oss.qualcomm.com>
To: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Prasad Sodagudi <prasad.sodagudi@oss.qualcomm.com>,
Nikunj Kela <quic_nkela@quicinc.com>,
Shazad Hussain <shazad.hussain@oss.qualcomm.com>
Subject: Re: [PATCH v5 2/3] arm64: dts: qcom: Introduce sa8255p SoC
Date: Wed, 25 Mar 2026 11:40:59 +0800 [thread overview]
Message-ID: <acNZSyygP64Z774H@QCOM-aGQu4IUr3Y> (raw)
In-Reply-To: <20260304-b4-scmi-upstream-v5-2-f8fc763d8da0@oss.qualcomm.com>
On Wed, Mar 04, 2026 at 08:28:29PM -0800, Deepti Jaggi wrote:
> From: Nikunj Kela <quic_nkela@quicinc.com>
>
> Introduce base device tree support for sa8255p Qualcomm's automotive
> infotainment SoC. The base dt file describes core SoC components- CPUs,
> CPU map, ipcc, QUP, geni UART, interrupt controller, TLMM, reserved
> memory, SMMU, firmware scm, scmi, watchdog, SRAM, PSCI, ufs, pcie, pmu
> nodes and enable booting to shell with ramdisk.
>
> The Qualcomm automotive sa8255p SoC utilizes firmware to configure
> platform resources such as clocks, interconnects, and TLMM. Device drivers
> request these resources through the SCMI power,reset and performance
> protocols. Assign each device driver a dedicated SCMI channel and Tx/Rx
> doorbells to support parallel resource requests and aggregation in the
> SCMI platform server. Operate the SCMI server stack in an SMP-enabled VM,
> using the Qualcomm SMC/HVC transport driver for communication.
>
> Group resource operations to improve abstraction and reduce the number of
> SCMI requests. Follow the SCMI-based resource management approach
> demonstrated by Qualcomm at LinaroConnect 2024.[1]
>
> Limit initial support to basic platform resources, serial console, ufs
> and pcie.Defer enabling USB, and Ethernet to subsequent updates.
>
> [1]: https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte
>
> Co-developed-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
> Signed-off-by: Shazad Hussain <shazad.hussain@oss.qualcomm.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> Co-developed-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sa8255p.dtsi | 4861 +++++++++++++++++++++++++++++++++
> 1 file changed, 4861 insertions(+)
Is my understanding correct that the following SoCs are all members of Lemans family?
- QCS9075/9100 (IQ9)
- SA8255P
- SA8775P
If so, does it make sense to apply DTS structure like below?
lemans.dtsi
|
|― lemans-iq9.dtsi
| |
| |― lemans-evk.dts (qcs9100-evk.dts ideally)
| |
| |― qcs9100-ride-r3.dts
| |
| |― qcs9100-ride.dts
|
|― lemans-sa8255p.dtsi
| |
| |― sa8255p-ride.dts
|
|― lemans-sa8775p.dtsi
|
|― sa8775p-ride-r3.dts
|
|― sa8775p-ride.dts
Shawn
next prev parent reply other threads:[~2026-03-25 3:41 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-05 4:28 [PATCH v5 0/3] arm64: dts: qcom: Introduce sa8255p platform device tree Deepti Jaggi
2026-03-05 4:28 ` [PATCH v5 1/3] dt-bindings: arm: qcom: add SA8255p Ride board Deepti Jaggi
2026-03-11 13:20 ` Bartosz Golaszewski
2026-03-05 4:28 ` [PATCH v5 2/3] arm64: dts: qcom: Introduce sa8255p SoC Deepti Jaggi
2026-03-11 13:31 ` Bartosz Golaszewski
2026-03-16 19:08 ` Deepti Jaggi
2026-03-11 13:41 ` Konrad Dybcio
2026-03-15 6:51 ` Shazad Hussain
2026-03-16 23:58 ` Deepti Jaggi
2026-03-23 11:07 ` Konrad Dybcio
2026-03-25 3:40 ` Shawn Guo [this message]
2026-03-05 4:28 ` [PATCH v5 3/3] arm64: dts: qcom: sa8255p: Enable sa8255p-ride board support Deepti Jaggi
2026-03-11 13:32 ` Bartosz Golaszewski
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