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Thu, 19 Nov 2020 01:46:48 GMT Sender: hemantk=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 8A815C43460; Thu, 19 Nov 2020 01:46:47 +0000 (UTC) Received: from [10.46.162.249] (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: hemantk) by smtp.codeaurora.org (Postfix) with ESMTPSA id CF83BC433C6; Thu, 19 Nov 2020 01:46:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org CF83BC433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=hemantk@codeaurora.org Subject: Re: [PATCH 2/8] mhi: pci-generic: Perform hard reset on remove To: Loic Poulain , manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org References: <1605279602-18749-1-git-send-email-loic.poulain@linaro.org> <1605279602-18749-3-git-send-email-loic.poulain@linaro.org> From: Hemant Kumar Message-ID: Date: Wed, 18 Nov 2020 17:46:46 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <1605279602-18749-3-git-send-email-loic.poulain@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Loic, On 11/13/20 6:59 AM, Loic Poulain wrote: > Ensure that the device is hard-reset on remove to restore its initial > state and avoid further issues on subsequent probe. > > This has been tested with Telit FN980m module. > > Signed-off-by: Loic Poulain > --- > drivers/bus/mhi/pci_generic.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c > index 13a7e4f..09c6b26 100644 > --- a/drivers/bus/mhi/pci_generic.c > +++ b/drivers/bus/mhi/pci_generic.c > @@ -15,6 +15,8 @@ > > #define MHI_PCI_DEFAULT_BAR_NUM 0 > > +#define DEV_RESET_REG (0xB0) > + > /** > * struct mhi_pci_dev_info - MHI PCI device specific information > * @config: MHI controller configuration > @@ -166,6 +168,11 @@ static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, > /* Nothing to do for now */ > } > > +static inline void mhi_pci_reset(struct mhi_controller *mhi_cntrl) > +{ > + writel(1, mhi_cntrl->regs + DEV_RESET_REG); > +} > + > static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, > unsigned int bar_num, u64 dma_mask) > { > @@ -329,6 +336,10 @@ static void mhi_pci_remove(struct pci_dev *pdev) > mhi_power_down(mhi_cntrl, true); > mhi_unprepare_after_power_down(mhi_cntrl); > mhi_unregister_controller(mhi_cntrl); > + > + /* MHI-layer reset could not be enough, always hard-reset the device */ > + mhi_pci_reset(mhi_cntrl); Referring to MHI spec: Hosts writes this register to trigger a reset. This can be used when the host detects a timeout in the MHI protocol and can use the reset as a last resort to recover the device. Host should first attempt an MHI Reset procedure before resetting the entire device. What issue are you facing which requires you to do full device reset ? Based on the spec recommendation, looks like this should be a last resort. Thanks, Hemant -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project