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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9b1f029890sm377563266b.56.2024.10.28.06.09.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Oct 2024 06:09:46 -0700 (PDT) Message-ID: Date: Mon, 28 Oct 2024 14:09:45 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: qcs615-ride: Enable PMIC peripherals To: Dmitry Baryshkov , Tingguo Cheng Cc: quic_fenglinw@quicinc.com, quic_tingweiz@quicinc.com, kernel@quicinc.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241028-adds-spmi-pmic-peripherals-for-qcs615-v3-0-f0778572ee41@quicinc.com> <20241028-adds-spmi-pmic-peripherals-for-qcs615-v3-2-f0778572ee41@quicinc.com> <38cceae8-5203-4057-bd8b-f20fe3656474@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: sUT2Dq7kq2WUD3QEcQogyxX6XJOePvRn X-Proofpoint-GUID: sUT2Dq7kq2WUD3QEcQogyxX6XJOePvRn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280106 On 28.10.2024 10:41 AM, Dmitry Baryshkov wrote: > On Mon, 28 Oct 2024 at 10:40, Tingguo Cheng wrote: >> >> >> >> On 10/28/2024 4:23 PM, Dmitry Baryshkov wrote: >>> On Mon, Oct 28, 2024 at 04:03:25PM +0800, Tingguo Cheng wrote: >>>> Enable PMIC and PMIC peripherals for qcs615-ride board. >>>> >>>> Signed-off-by: Tingguo Cheng >>>> --- >>>> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 15 +++++++++++++++ >>>> 1 file changed, 15 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>>> index ee6cab3924a6d71f29934a8debba3a832882abdd..37358f080827bbe4484c14c5f159e813810c2119 100644 >>>> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>>> @@ -6,6 +6,7 @@ >>>> >>>> #include >>>> #include "qcs615.dtsi" >>>> +#include "pm8150.dtsi" >>>> / { >>>> model = "Qualcomm Technologies, Inc. QCS615 Ride"; >>>> compatible = "qcom,qcs615-ride", "qcom,qcs615"; >>>> @@ -210,6 +211,20 @@ &rpmhcc { >>>> clocks = <&xo_board_clk>; >>>> }; >>>> >>>> +&pon { >>>> + /delete-property/ mode-bootloader; >>>> + /delete-property/ mode-recovery; >>> >>> Why? >> Because boot modes will be supported on PSCI module from another patch, >> reboot-modes are required to remove from PMIC side. Do we know whether the PSCI call does the same thing under the hood? Konrad