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Mon, 20 Apr 2026 23:06:11 -0700 (PDT) X-Received: by 2002:a05:6a00:4511:b0:82f:7762:3eb2 with SMTP id d2e1a72fcca58-82f8b507fdamr12071065b3a.17.1776751571216; Mon, 20 Apr 2026 23:06:11 -0700 (PDT) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f932dac13sm12018462b3a.35.2026.04.20.23.06.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2026 23:06:10 -0700 (PDT) Date: Tue, 21 Apr 2026 11:36:02 +0530 From: Abhinaba Rakshit To: Harshal Dev Cc: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Neeraj Soni , Kuldeep Singh , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v8 1/5] soc: qcom: ice: Add OPP-based clock scaling support for ICE Message-ID: References: <20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com> <20260409-enable-ice-clock-scaling-v8-1-ca1129798606@oss.qualcomm.com> <4528374d-8175-4a1c-859f-23ddf2bbef52@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <4528374d-8175-4a1c-859f-23ddf2bbef52@oss.qualcomm.com> X-Proofpoint-ORIG-GUID: pQiUfztBhLDJ1rQuc_wgMG39JMuTI7-l X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIxMDA1NyBTYWx0ZWRfXyw5YqtZoCtlC DLzM5MtDw2JVH5XYDLbwTUgz42pA+aKO0fhQr+ROgc4iCPi8QFvQkyVLJRN4l+EQWH7klvSlHgx rPQeSgySZ0cAGVrogV2POXT0jmTnE8TFBI2XIha3NN7tsX6X+i/IVC9yWGwKj3LBbuo8KwutvI5 rj4iiHrF6p3R5QDkUMvt9kSUKbl+Q79Db5lWNNzqsVL0bkfa5Rkt04B4gFw+2R6ZCrxnReD0Pua /Lz0iI/R/66oA19tQvmx525FSn+odZhhqvXoxgSqkWj42/aO3WCJIWREADoroDnle685egmihdf OoALXrT7A14PWCEWL8/omtl/AU8Ylw6EKMOoU8RsFm4GANeUdz/yXytyUM8MnMDdNDE1CSw9IKR DNh4yJn09HF2TW1NnBYTRFi6rCAIlEqj6sNbOJFV5lt7L30LWodu6tJF6CUHX0LFYRV8KfC5PSw 932XOOIg+Kmo0VAbxIg== X-Authority-Analysis: v=2.4 cv=XNMAjwhE c=1 sm=1 tr=0 ts=69e713d5 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=XGHNUSocF6D1puBBiEoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: pQiUfztBhLDJ1rQuc_wgMG39JMuTI7-l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-21_01,2026-04-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 clxscore=1015 phishscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210057 On Fri, Apr 17, 2026 at 06:55:14PM +0530, Harshal Dev wrote: > > > On 4/9/2026 5:14 PM, Abhinaba Rakshit wrote: > > Register optional operation-points-v2 table for ICE device > > during device probe. Attach the OPP-table with only the ICE > > core clock. Since, dtbinding is on a trasition phase to include > > iface clock and clock-names, attaching the opp-table to core clock > > remains options such that it does not cause probe failures. > > > > Introduce clock scaling API qcom_ice_scale_clk which scale ICE > > core clock based on the target frequency provided and if a valid > > OPP-table is registered. Use round_ceil passed to decide on the > > rounding of the clock freq against OPP-table. Clock scaling is > > disabled when a valid OPP-table is not registered. > > > > This ensures when an ICE-device specific OPP table is available, > > use the PM OPP framework to manage frequency scaling and maintain > > proper power-domain constraints. > > > > Also, ensure to drop the votes in suspend to prevent power/thermal > > retention. Subsequently restore the frequency in resume from > > core_clk_freq which stores the last ICE core clock operating frequency. > > > > Signed-off-by: Abhinaba Rakshit > > --- > > drivers/soc/qcom/ice.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++++++ > > include/soc/qcom/ice.h | 2 ++ > > 2 files changed, 94 insertions(+) > > > > diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c > > index bf4ab2d9e5c0360d8fe6135cc35f93b6b09e7a0e..9e869e6abc6300c7608b4d9a18e7f3e80c93f5e7 100644 > > --- a/drivers/soc/qcom/ice.c > > +++ b/drivers/soc/qcom/ice.c > > @@ -16,6 +16,7 @@ > > [..] > > > @@ -742,6 +800,40 @@ static int qcom_ice_probe(struct platform_device *pdev) > > if (IS_ERR(engine)) > > return PTR_ERR(engine); > > > > + /* qcom_ice_create() may return NULL if scm calls are not available */ > > + if (!engine) > > + return -EOPNOTSUPP; > > + > > + err = devm_pm_opp_set_clkname(&pdev->dev, "core"); > > + if (err && err != -ENOENT) { > > + dev_err(&pdev->dev, "Unable to set core clkname to OPP-table\n"); > > + return err; > > + } > > + > > + /* OPP table is optional */ > > + err = devm_pm_opp_of_add_table(&pdev->dev); > > + if (err && err != -ENODEV) { > > + dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); > > + return err; > > + } > > + > > + /* > > + * The OPP table is optional. devm_pm_opp_of_add_table() returns > > + * -ENODEV when no OPP table is present in DT, which is not treated > > + * as an error. Therefore, track successful OPP registration only > > + * when the return value is 0. > > + */ > > + engine->has_opp = (err == 0); > > + if (!engine->has_opp) > > + dev_info(&pdev->dev, "ICE OPP table is not registered, please update your DT\n"); > > + > > + /* > > + * Store the core clock rate for suspend resume cycles, > > + * against OPP aware DVFS operations. core_clk_freq will > > + * have a valid value only for non-legacy bindings. > > + */ > > + engine->core_clk_freq = clk_get_rate(engine->core_clk); > > + > > When you are calling 4-5 functions in a function, it's probably time to define another > function to keep things simple. Maybe qcom_ice_attach_opp_table(). > > Also, I still have issues with engine->has_opp = (err == 0), mostly because I don't > see this style used at other placed in the kernel. I would still suggest that you > make it simpler, but I won't hard-request it. > > /* The same explanatory comment as before */ > if (err == -ENODEV) > engine->has_opp = false; > dev_info(...); > else > engine->has_opp = true; > > With these optional suggestions, feel free to add: > > Reviewed-by: Harshal Dev Thanks for the review. Regarding the points you mentioned: At the moment, not much is happening here beyond registering the OPP table and caching the core clock rate. This is executed once per device probe, and the logic is fairly localized to the ICE probe path. Because of that, it didn’t feel like its reusable or demands its own helper. That said, I do see your point about modularity. If this logic grows further, or if we end up needing the same sequence elsewhere, I agree it would make sense to factor it out into a separate function at that time. Regarding engine->has_opp = (err == 0), I understand your concern. However, I intend to keep it this way, as it keeps the flow consise avoiding much of if-else branching and also serves the purpose. Abhinaba Rakshit