From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D9032143722; Wed, 29 Jan 2025 16:43:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169025; cv=none; b=L6EiBtmDbTtaM2jj9VBLcwIV42ofRaKdtyLJ1LFCEAaIVSyFPWwdlVaBpkl2LrxA0qSSPmfbyEvxZ/MVcZPu03WamwloDClroSlZe05vIpt/TCkufjTOAYhon/cG25c4HUx/L8QuU7mOHfl35AZTyMGlnlbWy1ABTPJ8aUwfAuk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738169025; c=relaxed/simple; bh=bjXQS+WjTj5gxQTd/SKBqciWrxIb/RWjnWTomQ1YQpc=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=NcXZjYhPAPpwfJSbF+V/jkIxXTt7Uy1m7GIMzl3vlgQGfjMjq6KISkfCwjPOuRXEX1vxwbPzPuTaK4YTZyrMUE4x4sYkqS/UCMooTvBm+uSJYGZdmG+RALmOpBujFVcarJy5vdVBLr2JqitBVuUaB+K5ZbgVHW33voKajPYspLQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F04791007; Wed, 29 Jan 2025 08:44:08 -0800 (PST) Received: from [10.1.196.57] (eglon.cambridge.arm.com [10.1.196.57]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1B1F53F63F; Wed, 29 Jan 2025 08:43:38 -0800 (PST) Message-ID: Date: Wed, 29 Jan 2025 16:43:34 +0000 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/5] arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists To: Douglas Anderson , Catalin Marinas , Will Deacon , Mark Rutland Cc: Roxana Bradescu , Julius Werner , bjorn.andersson@oss.qualcomm.com, Trilok Soni , linux-arm-msm@vger.kernel.org, Florian Fainelli , linux-arm-kernel@lists.infradead.org, Jeffrey Hugo , Scott Bauer , stable@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250107200715.422172-1-dianders@chromium.org> <20250107120555.v4.5.I4a9a527e03f663040721c5401c41de587d015c82@changeid> Content-Language: en-GB From: James Morse In-Reply-To: <20250107120555.v4.5.I4a9a527e03f663040721c5401c41de587d015c82@changeid> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Doug, On 07/01/2025 20:06, Douglas Anderson wrote: > When comparing to the ARM list [1], it appears that several ARM cores > were missing from the lists in spectre_bhb_loop_affected(). Add them. It's a moving target! > NOTE: for some of these cores it may not matter since other ways of > clearing the BHB may be used (like the CLRBHB instruction or ECBHB), > but it still seems good to have all the info from ARM's whitepaper > included. > > [1] https://developer.arm.com/Arm%20Security%20Center/Spectre-BHB > > > Fixes: 558c303c9734 ("arm64: Mitigate spectre style branch history side channels") > Cc: stable@vger.kernel.org Reviewed-by: James Morse Thanks! James