Re: [PATCH v3 5/9] drm/msm/dpu: Add SM6150 support

[fange zhang <quic_fangez@quicinc.com>]

On 2024/12/7 4:17, Abhinav Kumar wrote:
> 
> 
> On 11/22/2024 1:56 AM, Fange Zhang wrote:
>> From: Li Liu <quic_lliu6@quicinc.com>
>>
>> Add definitions for the display hardware used on the Qualcomm SM6150
>> platform.
>>
>> Signed-off-by: Li Liu <quic_lliu6@quicinc.com>
>> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com>
>> ---
>>   .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 263 +++++++++++ 
>> ++++++++++
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c     |   1 +
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |   1 +
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c            |   1 +
>>   4 files changed, 266 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/ 
>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
>> new file mode 100644
>> index 
>> 0000000000000000000000000000000000000000..e8b7f694b885d69a9bbfaa85b0faf0c7af677a75
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
>> @@ -0,0 +1,263 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights 
>> reserved.
>> + */
>> +
>> +#ifndef _DPU_5_3_SM6150_H
>> +#define _DPU_5_3_SM6150_H
>> +
>> +
> 
> <snip>
> 
>> +static const struct dpu_sspp_cfg sm6150_sspp[] = {
>> +    {
>> +        .name = "sspp_0", .id = SSPP_VIG0,
>> +        .base = 0x4000, .len = 0x1f0,
>> +        .features = VIG_SDM845_MASK,
> 
> This is not correct. Smartdma is supported on this chipset on both Vig 
> and DMA SSPPs.
> 
> Please use VIG_SDM845_MASK_SDMA and DMA_SDM845_MASK_SDMA respectively.
Got it, will replace them in next patch
> 
> 
>> +        .sblk = &dpu_vig_sblk_qseed3_2_4,
>> +        .xin_id = 0,
>> +        .type = SSPP_TYPE_VIG,
>> +        .clk_ctrl = DPU_CLK_CTRL_VIG0,
>> +    }, {
>> +        .name = "sspp_8", .id = SSPP_DMA0,
>> +        .base = 0x24000, .len = 0x1f0,
>> +        .features = DMA_SDM845_MASK,
>> +        .sblk = &dpu_dma_sblk,
>> +        .xin_id = 1,
>> +        .type = SSPP_TYPE_DMA,
>> +        .clk_ctrl = DPU_CLK_CTRL_DMA0,
>> +    }, {
>> +        .name = "sspp_9", .id = SSPP_DMA1,
>> +        .base = 0x26000, .len = 0x1f0,
>> +        .features = DMA_SDM845_MASK,
>> +        .sblk = &dpu_dma_sblk,
>> +        .xin_id = 5,
>> +        .type = SSPP_TYPE_DMA,
>> +        .clk_ctrl = DPU_CLK_CTRL_DMA1,
>> +    }, {
>> +        .name = "sspp_10", .id = SSPP_DMA2,
>> +        .base = 0x28000, .len = 0x1f0,
>> +        .features = DMA_CURSOR_SDM845_MASK_SDMA,
>> +        .sblk = &dpu_dma_sblk,
>> +        .xin_id = 9,
>> +        .type = SSPP_TYPE_DMA,
>> +        .clk_ctrl = DPU_CLK_CTRL_DMA2,
>> +    }, {
>> +        .name = "sspp_11", .id = SSPP_DMA3,
>> +        .base = 0x2a000, .len = 0x1f0,
>> +        .features = DMA_CURSOR_SDM845_MASK_SDMA,
>> +        .sblk = &dpu_dma_sblk,
>> +        .xin_id = 13,
>> +        .type = SSPP_TYPE_DMA,
>> +        .clk_ctrl = DPU_CLK_CTRL_DMA3,
>> +    },
>> +};
>> +
> 
> <snip>