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Tue, 26 May 2026 05:35:18 -0700 (PDT) Date: Tue, 26 May 2026 14:34:46 +0200 From: Stephan Gerhold To: Maulik Shah Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, Sneh Mankad Subject: Re: [PATCH v2 3/8] irqchip/qcom-pdc: Remove pdc_enable_intr() wrapper Message-ID: References: <20260526-hamoa_pdc-v2-0-f6857af1ce91@oss.qualcomm.com> <20260526-hamoa_pdc-v2-3-f6857af1ce91@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260526-hamoa_pdc-v2-3-f6857af1ce91@oss.qualcomm.com> On Tue, May 26, 2026 at 04:24:39PM +0530, Maulik Shah wrote: > pdc->enable_intr() function already points to respective version > specific enable function. pdc_enable_intr() now only kept as wrapper. > Remove the wrapper and invoke pdc->enable_intr() from caller. > > Locking in pdc_enable_intr() applies lock to all pdc->enable_intr() > however its only required for pdc_enable_intr_bank() which uses > a shared bank across all interrupts. pdc_enable_intr_cfg() do not > required locking as IRQ_CFG registers are one per interrupt. Move > locking accordingly. Well, pdc_enable_intr_cfg() is still a read-modify-write. If two CPUs read IRQ_i_CFG at the same time and modify different bits (e.g. enable and type bits) then write back the modified register one of the modifications will get lost. Can we be sure that this won't happen? Perhaps we can since PDC has IRQCHIP_SET_TYPE_MASKED, but personally I would keep the lock there to be sure, especially with the new GPIO operations you add that also read-modify-write the same register.. Thanks, Stephan