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Sun, 14 Jun 2026 20:54:15 -0700 (PDT) Received: from oss.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-37a262adbe3sm10477963a91.13.2026.06.14.20.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Jun 2026 20:54:15 -0700 (PDT) Date: Mon, 15 Jun 2026 09:24:07 +0530 From: Mohd Ayaan Anwar To: Andrew Lunn Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Bjorn Andersson , Konrad Dybcio , Maxime Coquelin , Alexandre Torgue , Russell King , linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH RFC 3/9] net: stmmac: qcom-ethqos: fix RGMII_ID mode to use DLL bypass Message-ID: References: <20260612-shikra_ethernet-v1-0-f0f4a1d19929@oss.qualcomm.com> <20260612-shikra_ethernet-v1-3-f0f4a1d19929@oss.qualcomm.com> <42355330-c22a-4fce-98ab-dc22b321ff16@lunn.ch> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <42355330-c22a-4fce-98ab-dc22b321ff16@lunn.ch> X-Authority-Analysis: v=2.4 cv=HuxG3UTS c=1 sm=1 tr=0 ts=6a2f7768 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=kj9zAlcOel0A:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=h-cV_6-i1hGX5lmYmEcA:9 a=CjuIK1q_8ugA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: pa6cmoSU7dhgE-23YYAxAWN6i0c_X6VC X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDAzNyBTYWx0ZWRfX4sb8lOctmFI+ XhBY9yxPRHNrcGKUkQV7l9Z4r5ghoaIrUEaTm1WY5ZNprVLZHYt+VLQ7NsYhcsgpLKKJ96y9fjI 9UVP0P5Sa/xBox5qxOD5wHBuj2Jk1qo= X-Proofpoint-GUID: pa6cmoSU7dhgE-23YYAxAWN6i0c_X6VC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDAzNyBTYWx0ZWRfXyawVR9wb8j/9 fMu7gYb90aiGjiDsWhzHf5FvUNdgEPa1lvXUEvBRpmIYbh2xODIiWOurNS1uphHbWb06HgwTLNh FQMh0VMMK4xjEsHu2DbpwKit6XoQZOosT1f0STkd818KBklImRYhRplYNrt3ZFhzgRilUi767Ll EUiIh8i1+LCHL9bMWZiPksNZqPsI+d1yqwuaMQZB75VHA1DpCSvrZlDu3Lb1LIk6egkXDhMol/J O8TH1K2jdfbAO/aDZty94RiDMqbl2ha4qT+C4ysXv/iY0H3kj2t0VFA1IjJLW/dkOpjqoFvN18w OrwOkKiu/94QYJdr0KSlLPNaKoMolgQm5pQDS167evxQuBZxOYMIlTCKMmyw2FfshgWFYpnyxqe MVop47tGPeSb2xzqTXseRazlGl5jBSJwhTGIJPw1QXaOTFMWoH7laOFdhT31iMaD1O5QeI2BMIn W7fTIYQH5oOVTnWSt+w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_01,2026-06-12_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 adultscore=0 impostorscore=0 priorityscore=1501 phishscore=0 clxscore=1015 spamscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150037 Hello Andrew, On Thu, Jun 11, 2026 at 10:54:37PM +0200, Andrew Lunn wrote: > On Fri, Jun 12, 2026 at 12:06:59AM +0530, Mohd Ayaan Anwar wrote: > > When "rgmii-id" is selected the PHY supplies both TX and RX delays, so > > the MAC must not add its own. The driver currently falls through to the > > generic DLL initialisation path which programs it to add a delay. > > > > Power down the DLL and set DDR bypass mode for RGMII_ID, then program > > the IO_MACRO via a new ethqos_rgmii_id_macro_init() helper. Also fix > > ethqos_set_clk_tx_rate() to not double the clock rate in bypass mode at > > 100M/10M, and remove RGMII_ID from the phase-shift suppression in > > ethqos_rgmii_macro_init() since RGMII_ID no longer reaches that path. > > I'm curious how this works at the moment? Do no boards make use of > RGMII ID? Are all current boards broken? Searching through the DTS, I found that we have two boards using "rgmii" (qcs404-evb-4000.dts and sa8155-adp.dts) and another board using "rgmii-txid" (sa8540p-ride.dts). No board which uses RGMII ID. I don't think any of these boards have extra long wires which would add PCB level delay. They are against the netdev definitions for "rgmii" and "rgmii-txid". But the first two boards should still be working fine since the current driver programs the IO_MACRO to add the delay when operating in RGMII mode. I am not sure about the last board. I went through the different versions of the ETHQOS programming guide, and it should reliably support either only MAC side Rx/Tx delay -or- bypass mode (no MAC side delay), with each having different clock requirements. Ayaan