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Mon, 06 Jul 2026 05:55:37 -0700 (PDT) Date: Mon, 6 Jul 2026 14:55:26 +0200 From: Stephan Gerhold To: Miquel Raynal Cc: Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-mtd@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: Re: [PATCH 0/4] mtd: rawnand: qcom: Add MDM9607 Message-ID: References: <20260608-qcom-nandc-mdm9607-v1-0-4639a0492274@linaro.org> <4kdjxrn3bxg7rhkdovidxv2b2f6evnknng7gjtbz7pahyqaakh@qkgxaz6xlav2> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <4kdjxrn3bxg7rhkdovidxv2b2f6evnknng7gjtbz7pahyqaakh@qkgxaz6xlav2> Hi Miquèl, On Mon, Jun 29, 2026 at 05:46:57PM +0200, Manivannan Sadhasivam wrote: > On Mon, Jun 08, 2026 at 03:20:21PM +0200, Stephan Gerhold wrote: > > MDM9607 has QPIC v1.5 that supports the OP_PAGE_READ_ONFI_READ command, but > > is missing the rest of the hardware changes in QPIC v2. There is also only > > a single clock that can be controlled using the RPM firmware. Document and > > add the new qcom,mdm9607-nand compatible for this setup. > > > > Signed-off-by: Stephan Gerhold > > You could ammend patch 1's commit message with the information I shared in the > reply. But nevertheless: > > Reviewed-by: Manivannan Sadhasivam > Do you want me to resend the series with patch 1 commit message adjusted? There were no other changes requested as far as I can tell. I think the current commit message there is fine, especially if you add the Link: tag during applying. The extra context will be there. If you want me to resend, I would just replace the second paragraph in patch 1 with the following: --- On MDM9607 and other recent SoCs, the QPIC hardware requires 3 clocks (ahb, core, aon). However, the access to these clocks is restricted to the RPM firmware that controls the shared power resources for the whole SoC. The clocks cannot be controlled separately, there is only a single RPM_SMD_QPIC_CLK clock that implicitly enables all of the 3 clocks. The only exception to this are some IPQ* SoC that are not using RPM, there the clocks are directly controlled by the kernel via the clock controller (GCC). Require only one clock in the dt-bindings for MDM9607 to avoid having to define dummy clock entries. --- Thanks, Stephan