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Sat, 17 Oct 2026 09:05:04 -0700 (PDT) Received: from oss.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3608308a87csm29199920eec.28.2026.10.17.09.04.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2026 09:05:03 -0700 (PDT) Date: Sat, 17 Oct 2026 21:34:53 +0530 From: Mohd Ayaan Anwar To: Andrew Lunn Cc: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Heiner Kallweit , Russell King , Richard Cochran , Bjorn Andersson , Konrad Dybcio , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin , Lorenzo Bianconi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH net-next v3 4/9] net: stmmac: qcom-ethqos: fix RGMII_ID mode to use DLL bypass Message-ID: References: <20261017-shikra_ethernet-v3-0-26a8beb44b8f@oss.qualcomm.com> <20261017-shikra_ethernet-v3-4-26a8beb44b8f@oss.qualcomm.com> <17aea8bf-490f-4006-880f-1999aed1df59@lunn.ch> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <17aea8bf-490f-4006-880f-1999aed1df59@lunn.ch> X-Authority-Analysis: v=2.4 cv=BNUmP1QG c=1 sm=1 tr=0 ts=6ad39cb2 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=2_h2fYecv1F4Ojg9QoMA:9 a=CjuIK1q_8ugA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: gT2OOQZV-Th2N_oEF8tu9ddcga25y0tW X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE3MDA2NCBTYWx0ZWRfXxkSXB/p30AFg tgBumqhi5PyvC8o+T/TEHCx3IvuOiRvSotkvTcp5PtIZQ3+qCl5pYYXIQNBYX8V8q4MoTK1JrTj eTV1SdOAm1+xshZn1FyDbv1tZpGh/CM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE3MDA2NCBTYWx0ZWRfX56FYN9uf5s8G A8NETnfFSVoZwuNRwzqceUQ7K2diiwwQkN+S032603jZD3v2MCYYv/jJ1E5Q04m5DrYKlyZJMjV CW8VbO2u3oozv15F/Papru9M1/g4KKmYstABjqCUPIVpi0dQdRJhQGe4yCPw745FYWq3pREajMs zzdw6xtGZ8Z02JGJAXTx3xgwrvwzl0nhQ69SgtBv6bk0xyl0uNv4m4lrALf7nf1R/AmzA3noWSC qEtQXATb66J7Sf+uS7Sq6FMsGSxWiE8OD31Ve3htSBuFZHmFnON1XVvpaAZVWR+cbUxvZt3/o39 w+AZTTSQ7ytbzTAurWd694LnjR6Y4Aa3rNimArt6XceFHiLB2DSHy7udwidxl38IKa/OFZwk9GN 3/Dx0usW/Z/TFGncgoEHpSjDIi7KvN48Q/ja0dVXNvyaI3CyqJunR8DUY1+I47kgOwzEOYLHzCC U4O0XVRZYqXOJoN6y7g== X-Proofpoint-ORIG-GUID: gT2OOQZV-Th2N_oEF8tu9ddcga25y0tW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-17_04,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610170064 On Sat, Oct 17, 2026 at 04:00:27PM +0200, Andrew Lunn wrote: > On Sat, Oct 17, 2026 at 03:15:15PM +0530, Mohd Ayaan Anwar wrote: > > When "rgmii-id" is selected the PHY supplies both TX and RX delays, so > > the MAC must not add its own. The driver currently falls through to the > > generic DLL initialisation path which programs it to add a delay. > > > > Power down the DLL and set DDR bypass mode for RGMII_ID, then program > > the IO_MACRO via a new ethqos_rgmii_id_macro_init() helper. Also fix > > ethqos_set_clk_tx_rate() to not double the clock rate in bypass mode at > > 100M/10M, and remove RGMII_ID from the phase-shift suppression in > > ethqos_rgmii_macro_init() since RGMII_ID no longer reaches that path. > > How many different boards have you tested this on? How confident are > you there will not be regressions? > Apart from the new compatible, I have tested this on three different board designs of the QCS615 SoC. The EMAC on it is identical to the "qcom,qcs404-ethqos" version. Two of the boards have the Microchip KSZ9031 PHY while the third has the TI DP83867 PHY. > Since you are adding a new compatible "qcom,shikra-ethqos", you could > limit the change in behaviour to just this. > That sounds like a better idea. I will restrict the new sequence to just "qcom,shikra-ethqos" and "qcom,qcs404-ethqos" using something like data->phy_managed_delays = true. I will change the warning patch to also check for this boolean, so any users of "qcom,qcs404-ethqos" can be notified. The two other RGMII designs ("qcom,qcs404-ethqos" and "qcom,sc8280xp-ethqos") can continue using the legacy flow. Ayaan