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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ebccfaecfbsm9373513a12.41.2025.03.26.06.17.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Mar 2025 06:17:03 -0700 (PDT) Message-ID: Date: Wed, 26 Mar 2025 14:17:00 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 0/5] Add snps,dis_u3_susphy_quirk for some QC targets To: Bjorn Andersson , Konrad Dybcio Cc: Prashanth K , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250325123019.597976-1-prashanth.k@oss.qualcomm.com> <7029a455-47be-475d-b429-98031d227653@oss.qualcomm.com> <5k45tcntn2bhxqt35quzfm2dsq6eug3hgqdcrta25oy47zuqja@4jclvspwob5x> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <5k45tcntn2bhxqt35quzfm2dsq6eug3hgqdcrta25oy47zuqja@4jclvspwob5x> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: ov0xFzs1l2-tE6Aqo0O-QxQThv3343xX X-Proofpoint-GUID: ov0xFzs1l2-tE6Aqo0O-QxQThv3343xX X-Authority-Analysis: v=2.4 cv=QLZoRhLL c=1 sm=1 tr=0 ts=67e3fe51 cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=xMnwRdS-aKneeMBeM7YA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-26_06,2025-03-26_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 adultscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503260081 On 3/25/25 11:10 PM, Bjorn Andersson wrote: > On Tue, Mar 25, 2025 at 05:31:28PM +0100, Konrad Dybcio wrote: >> On 3/25/25 4:01 PM, Prashanth K wrote: >>> >>> >>> On 25-03-25 08:11 pm, Konrad Dybcio wrote: >>>> On 3/25/25 1:30 PM, Prashanth K wrote: >>>>> During device mode initialization on certain QC targets, before the >>>>> runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} >>>>> register write fails. As a result, GEVTADDR registers are still 0x0. >>>>> Upon setting runstop bit, DWC3 controller attempts to write the new >>>>> events to address 0x0, causing an SMMU fault and system crash. More >>>>> info about the crash at [1]. >>>>> >>>>> This was initially observed on SM8450 and later reported on few >>>>> other targets as well. As suggested by Qualcomm HW team, clearing >>>>> the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register >>>>> write failures. Address this by setting the snps,dis_u3_susphy_quirk >>>>> to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested >>>>> on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year >>>>> and hasn't exhibited any side effects. >>>>> >>>>> [1]: https://lore.kernel.org/all/fa94cbc9-e637-ba9b-8ec8-67c6955eca98@quicinc.com/ >>>>> >>>>> Prashanth K (3): >>>>> arm64: dts: qcom: sm8150: Add snps,dis_u3_susphy_quirk >>>>> arm64: dts: qcom: sm8350: Add snps,dis_u3_susphy_quirk >>>>> arm64: dts: qcom: sm8450: Add snps,dis_u3_susphy_quirk >>>>> >>>>> Pratham Pratap (2): >>>>> arm64: dts: qcom: qcs615: Add snps,dis_u3_susphy_quirk >>>>> arm64: dts: qcom: qdu1000: Add snps,dis_u3_susphy_quirk >>>> >>>> Are there more targets affected, from the list of the ones currently >>>> supported upstream? >>>> >>>> Konrad >>> >>> My initial plan was to add it for all the QC platforms, but wasn't >>> confident enough about it. Because we have seen the issue only on these >>> targets and hence tested only on these. >> >> Okay, let's proceed with these and in the meantime please query internally >> whether it could be applicable to others too >> > > But if it applies to all qcom targets, wouldn't it make more sense to > add the property in the qcom glue driver? If we did that and the issue was ever fixed in future hw, we'd have to either re-add this patchset again or invent a snps,*en*_u3_susphy_quirk Konrad