Re: [bug report] drm/msm/a6xx: Fix llcc configuration for a660 gpu

[Akhil P Oommen <akhilpo@codeaurora.org>]

On 10/12/2021 3:30 PM, Dan Carpenter wrote:
> Hello Akhil P Oommen,
> 
> The patch a6f24383f6c0: "drm/msm/a6xx: Fix llcc configuration for
> a660 gpu" from Jul 30, 2021, leads to the following Smatch static
> checker warning:
> 
> 	drivers/gpu/drm/msm/adreno/a6xx_gpu.c:1480 a6xx_llc_activate()
> 	error: uninitialized symbol 'gpu_scid'.
> 
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>      1423 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
>      1424 {
>      1425         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
>      1426         struct msm_gpu *gpu = &adreno_gpu->base;
>      1427         u32 gpu_scid, cntl1_regval = 0;
>      1428
>      1429         if (IS_ERR(a6xx_gpu->llc_mmio))
>      1430                 return;
>      1431
>      1432         if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
>      1433                 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
>      1434
>      1435                 gpu_scid &= 0x1f;
>      1436                 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) |
>      1437                                (gpu_scid << 15) | (gpu_scid << 20);
>      1438         }
> 
> gpu_scid not initialized on the else path.
> 
>      1439
>      1440         /*
>      1441          * For targets with a MMU500, activate the slice but don't program the
>      1442          * register.  The XBL will take care of that.
>      1443          */
>      1444         if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {
>      1445                 if (!a6xx_gpu->have_mmu500) {
>      1446                         u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);
>      1447
>      1448                         gpuhtw_scid &= 0x1f;
>      1449                         cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid);
>      1450                 }
>      1451         }
>      1452
>      1453         if (!cntl1_regval)
>      1454                 return;
>      1455
>      1456         /*
>      1457          * Program the slice IDs for the various GPU blocks and GPU MMU
>      1458          * pagetables
>      1459          */
>      1460         if (!a6xx_gpu->have_mmu500) {
>      1461                 a6xx_llc_write(a6xx_gpu,
>      1462                         REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval);
>      1463
>      1464                 /*
>      1465                  * Program cacheability overrides to not allocate cache
>      1466                  * lines on a write miss
>      1467                  */
>      1468                 a6xx_llc_rmw(a6xx_gpu,
>      1469                         REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03);
>      1470                 return;
>      1471         }
>      1472
>      1473         gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval);
>      1474
>      1475         /* On A660, the SCID programming for UCHE traffic is done in
>      1476          * A6XX_GBIF_SCACHE_CNTL0[14:10]
>      1477          */
>      1478         if (adreno_is_a660_family(adreno_gpu))
>      1479                 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) |
> --> 1480                         (1 << 8), (gpu_scid << 10) | (1 << 8));
>                                              ^^^^^^^^^^^^^^
> Used here.
> 
>      1481 }
> 
> regards,
> dan carpenter
> 

Thanks, Dan. I will fix this in the stack I share.

-Akhil.