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Fri, 13 Dec 2024 03:05:36 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BD35aJ3007215 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Dec 2024 03:05:36 GMT Received: from hu-pkondeti-hyd (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 12 Dec 2024 19:05:30 -0800 Date: Fri, 13 Dec 2024 08:35:27 +0530 From: Pavan Kondeti To: Mark Rutland CC: Marc Zyngier , Pavan Kondeti , Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , "Abhinav Kumar" , Dmitry Baryshkov , Marijn Suijten , David Airlie , "Simona Vetter" , Elliot Berman , , , , , Subject: Re: [PATCH] drm/msm/a6xx: Skip gpu secure fw load in EL2 mode Message-ID: References: <20241209-drm-msm-kvm-support-v1-1-1c983a8a8087@quicinc.com> <87ed2fs03w.wl-maz@kernel.org> <92cee905-a505-4ce9-9bbc-6fba4cea1d80@quicinc.com> <86sequsdtp.wl-maz@kernel.org> <87bjxhs2t7.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: dOH1GB_cEQesfUdqXmPeq8eFmXp0QQAP X-Proofpoint-ORIG-GUID: dOH1GB_cEQesfUdqXmPeq8eFmXp0QQAP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 clxscore=1011 impostorscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412130022 On Thu, Dec 12, 2024 at 10:40:46AM +0000, Mark Rutland wrote: > On Thu, Dec 12, 2024 at 08:50:12AM +0000, Marc Zyngier wrote: > > On Thu, 12 Dec 2024 05:31:00 +0000, > > Pavan Kondeti wrote: > > > > > > On Wed, Dec 11, 2024 at 10:40:02AM +0000, Marc Zyngier wrote: > > > > On Wed, 11 Dec 2024 00:37:34 +0000, > > > > Pavan Kondeti wrote: > > > > > > > > > > On Tue, Dec 10, 2024 at 09:24:03PM +0000, Marc Zyngier wrote: > > > > > > > +static int a6xx_switch_secure_mode(struct msm_gpu *gpu) > > > > > > > +{ > > > > > > > + int ret; > > > > > > > + > > > > > > > +#ifdef CONFIG_ARM64 > > > > > > > + /* > > > > > > > + * We can access SECVID_TRUST_CNTL register when kernel is booted in EL2 mode. So, use it > > > > > > > + * to switch the secure mode to avoid the dependency on zap shader. > > > > > > > + */ > > > > > > > + if (is_kernel_in_hyp_mode()) > > > > > > > + goto direct_switch; > > > > > > > > > > > > No, please. To check whether you are *booted* at EL2, you need to > > > > > > check for is_hyp_available(). Whether the kernel runs at EL1 or EL2 is > > > > > > none of the driver's business, really. This is still absolutely > > > > > > disgusting from an abstraction perspective, but I guess we don't have > > > > > > much choice here. > > > > > > > > > > > > > > > > Thanks Marc. Any suggestions on how we can make is_hyp_mode_available() > > > > > available for modules? Do you prefer exporting > > > > > kvm_protected_mode_initialized and __boot_cpu_mode symbols directly or > > > > > try something like [1]? > > > > > > > > Ideally, neither. These were bad ideas nine years ago, and they still > > > > are. The least ugly hack I can come up with is the patch below, and > > > > you'd write something like: > > > > > > > > if (cpus_have_cap(ARM64_HAS_EL2_OWNERSHIP)) > > > > blah(); > > > > > > > > This is obviously completely untested. > > > > > > > > > > I have tested your patch. It works as intended. Thanks Marc. > > > > Note that you will probably get some push-back from the arm64 > > maintainers on this front, because this is a fairly incomplete (and > > fragile) solution. > > > > It would be much better if the discriminant came from the device tree. > > After all, the hypervisor is fscking-up^W^Wchanging the programming > > model of the GPU, and that should be reflected in the DT. Because for > > all intent and purposes, this is not the same hardware anymore. > > FWIW I agree 100%, this should be described in DT. > > The cpucap doesn't describe the actual property we care about, and it > cannot in general (e.g. for nested virt). I would strongly prefer to not > have that as it's setting ourselves up for failure. > Thanks for the feedback. I understand that EL2 detection in kernel is not going to cover cases like bare metal EL1, nested virtualization. We plan to take the DT approach. Thanks, Pavan