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[66.131.184.68]) by smtp.gmail.com with ESMTPSA id q123sm12890805qke.28.2020.11.16.09.55.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Nov 2020 09:55:57 -0800 (PST) Subject: Re: [RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance To: Rob Clark , Christoph Hellwig , Jordan Crouse Cc: freedreno , Sean Paul , David Airlie , Daniel Vetter , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list References: <20201114151717.5369-1-jonathan@marek.ca> <20201114151717.5369-5-jonathan@marek.ca> <20201114162406.GC24411@lst.de> <50ddcadb-c630-2ef6-cdc4-724d9823fba7@marek.ca> <20201116173346.GA24173@lst.de> From: Jonathan Marek Message-ID: Date: Mon, 16 Nov 2020 12:52:41 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 11/16/20 12:50 PM, Rob Clark wrote: > On Mon, Nov 16, 2020 at 9:33 AM Christoph Hellwig wrote: >> >> On Sat, Nov 14, 2020 at 03:07:20PM -0500, Jonathan Marek wrote: >>> qcom's vulkan driver has nonCoherentAtomSize=1, and it looks like >>> dma_sync_single_for_cpu() does deal in some way with the partial cache line >>> case, although I'm not sure that means we can have a nonCoherentAtomSize=1. >> >> No, it doesn't. You need to ensure ownership is managed at >> dma_get_cache_alignment() granularity. > > my guess is nonCoherentAtomSize=1 only works in the case of cache > coherent buffers > nonCoherentAtomSize doesn't apply to coherent memory (as the name implies), I guess qcom's driver is just wrong about having nonCoherentAtomSize=1. Jordan just mentioned there is at least one conformance test for this, I wonder if it just doesn't test it well enough, or just doesn't test the non-coherent memory type?