[PATCH v4 1/4] drm/msm/dpu: re-introduce dpu core revision to the catalog

[PATCH v4 1/4] drm/msm/dpu: re-introduce dpu core revision to the catalog

[Abhinav Kumar]

Introduce the dpu core revision back as an entry to the catalog so that
we can just use dpu revision checks and enable those bits which
should be enabled unconditionally and not controlled by a catalog
and also simplify the changes to do something like:

if (dpu_core_revision > xxxxx && dpu_core_revision < xxxxx)
   enable the bit;

Since dpu's major and minor versions are now separate fields, lets
drop all the DPU_HW_VER macros.

changes in v4:
	- removed hex prefix from the revisions
	- updated the commit text to move some parts to cover letter
	- rebased and added support for sm6125 into this
	- introduce struct dpu_mdss_version to hold the core revision

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
---
 .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h  |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h  |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h  |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h  |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h  |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h  |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h  |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h  |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h  |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h  |  6 ++++++
 .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h    |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h  |  6 ++++++
 .../drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h  |  6 ++++++
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h  | 17 +++++++++++++++--
 17 files changed, 111 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 7d87dc2d7b1b..b5fbac55f127 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -315,7 +315,13 @@ static const struct dpu_perf_cfg msm8998_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version msm8998_mdss_ver = {
+	.core_major_ver = 3,
+	.core_minor_ver = 0,
+};
+
 const struct dpu_mdss_cfg dpu_msm8998_cfg = {
+	.mdss_ver = &msm8998_mdss_ver,
 	.caps = &msm8998_dpu_caps,
 	.ubwc = &msm8998_ubwc_cfg,
 	.mdp = &msm8998_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 87459cf40895..8000b870d3a7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -332,7 +332,13 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sdm845_mdss_ver = {
+	.core_major_ver = 4,
+	.core_minor_ver = 0,
+};
+
 const struct dpu_mdss_cfg dpu_sdm845_cfg = {
+	.mdss_ver = &sdm845_mdss_ver,
 	.caps = &sdm845_dpu_caps,
 	.ubwc = &sdm845_ubwc_cfg,
 	.mdp = &sdm845_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 96c542d620f1..7ce2d69d28f6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -375,7 +375,13 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sm8150_mdss_ver = {
+	.core_major_ver = 5,
+	.core_minor_ver = 0,
+};
+
 const struct dpu_mdss_cfg dpu_sm8150_cfg = {
+	.mdss_ver = &sm8150_mdss_ver,
 	.caps = &sm8150_dpu_caps,
 	.ubwc = &sm8150_ubwc_cfg,
 	.mdp = &sm8150_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 4edc1060f05c..cea005382456 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -402,7 +402,13 @@ static const struct dpu_perf_cfg sc8180x_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sc8180x_mdss_ver = {
+	.core_major_ver = 5,
+	.core_minor_ver = 1,
+};
+
 const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
+	.mdss_ver = &sc8180x_mdss_ver,
 	.caps = &sc8180x_dpu_caps,
 	.ubwc = &sc8180x_ubwc_cfg,
 	.mdp = &sc8180x_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
index b3bfb897327b..5fddfcce6288 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -200,7 +200,13 @@ static const struct dpu_perf_cfg sm6125_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sm6125_mdss_ver = {
+	.core_major_ver = 5,
+	.core_minor_ver = 4,
+};
+
 const struct dpu_mdss_cfg dpu_sm6125_cfg = {
+	.mdss_ver = &sm6125_mdss_ver,
 	.caps = &sm6125_dpu_caps,
 	.ubwc = &sm6125_ubwc_cfg,
 	.mdp = &sm6125_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index f8910dbc1952..893d1271fb71 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -390,7 +390,13 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sm8250_mdss_ver = {
+	.core_major_ver = 6,
+	.core_minor_ver = 0,
+};
+
 const struct dpu_mdss_cfg dpu_sm8250_cfg = {
+	.mdss_ver = &sm8250_mdss_ver,
 	.caps = &sm8250_dpu_caps,
 	.ubwc = &sm8250_ubwc_cfg,
 	.mdp = &sm8250_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 8c046eacec7c..61118f648cbc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -204,7 +204,13 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sc7180_mdss_ver = {
+	.core_major_ver = 6,
+	.core_minor_ver = 2,
+};
+
 const struct dpu_mdss_cfg dpu_sc7180_cfg = {
+	.mdss_ver = &sc7180_mdss_ver,
 	.caps = &sc7180_dpu_caps,
 	.ubwc = &sc7180_ubwc_cfg,
 	.mdp = &sc7180_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 473cdbace322..c0d7bb930e8a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -136,7 +136,13 @@ static const struct dpu_perf_cfg sm6115_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sm6115_mdss_ver = {
+	.core_major_ver = 6,
+	.core_minor_ver = 3,
+};
+
 const struct dpu_mdss_cfg dpu_sm6115_cfg = {
+	.mdss_ver = &sm6115_mdss_ver,
 	.caps = &sm6115_dpu_caps,
 	.ubwc = &sm6115_ubwc_cfg,
 	.mdp = &sm6115_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index ac716c8dbd7f..11c50aa5034b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -207,7 +207,13 @@ static const struct dpu_perf_cfg sm6350_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sm6350_mdss_ver = {
+	.core_major_ver = 6,
+	.core_minor_ver = 4,
+};
+
 const struct dpu_mdss_cfg dpu_sm6350_cfg = {
+	.mdss_ver = &sm6350_mdss_ver,
 	.caps = &sm6350_dpu_caps,
 	.ubwc = &sm6350_ubwc_cfg,
 	.mdp = &sm6350_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 7d9fdd807695..2182939bc026 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -126,7 +126,13 @@ static const struct dpu_perf_cfg qcm2290_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version qcm2290_mdss_ver = {
+	.core_major_ver = 6,
+	.core_minor_ver = 5,
+};
+
 const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
+	.mdss_ver = &qcm2290_mdss_ver,
 	.caps = &qcm2290_dpu_caps,
 	.ubwc = &qcm2290_ubwc_cfg,
 	.mdp = &qcm2290_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 5f36f9468853..f0c0aa90f82e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -146,7 +146,13 @@ static const struct dpu_perf_cfg sm6375_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sm6375_mdss_ver = {
+	.core_major_ver = 6,
+	.core_minor_ver = 9,
+};
+
 const struct dpu_mdss_cfg dpu_sm6375_cfg = {
+	.mdss_ver = &sm6375_mdss_ver,
 	.caps = &sm6375_dpu_caps,
 	.ubwc = &sm6375_ubwc_cfg,
 	.mdp = &sm6375_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index b22e6b97c993..2460ced03610 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -383,7 +383,13 @@ static const struct dpu_perf_cfg sm8350_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sm8350_mdss_ver = {
+	.core_major_ver = 7,
+	.core_minor_ver = 0,
+};
+
 const struct dpu_mdss_cfg dpu_sm8350_cfg = {
+	.mdss_ver = &sm8350_mdss_ver,
 	.caps = &sm8350_dpu_caps,
 	.ubwc = &sm8350_ubwc_cfg,
 	.mdp = &sm8350_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 4b2cc62b07ea..a8dea8f27c41 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -252,7 +252,13 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sc7280_mdss_ver = {
+	.core_major_ver = 7,
+	.core_minor_ver = 2,
+};
+
 const struct dpu_mdss_cfg dpu_sc7280_cfg = {
+	.mdss_ver = &sc7280_mdss_ver,
 	.caps = &sc7280_dpu_caps,
 	.ubwc = &sc7280_ubwc_cfg,
 	.mdp = &sc7280_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index ec959f85ae2a..397fe01125dd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -445,7 +445,13 @@ static const struct dpu_perf_cfg sc8280xp_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sc8280xp_mdss_ver = {
+	.core_major_ver = 8,
+	.core_minor_ver = 0,
+};
+
 const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
+	.mdss_ver = &sc8280xp_mdss_ver,
 	.caps = &sc8280xp_dpu_caps,
 	.ubwc = &sc8280xp_ubwc_cfg,
 	.mdp = &sc8280xp_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 98a4aaef94d2..90a8461911c8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -406,7 +406,13 @@ static const struct dpu_perf_cfg sm8450_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sm8450_mdss_ver = {
+	.core_major_ver = 8,
+	.core_minor_ver = 1,
+};
+
 const struct dpu_mdss_cfg dpu_sm8450_cfg = {
+	.mdss_ver = &sm8450_mdss_ver,
 	.caps = &sm8450_dpu_caps,
 	.ubwc = &sm8450_ubwc_cfg,
 	.mdp = &sm8450_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 7de9eccf9181..c9252528136d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -420,7 +420,13 @@ static const struct dpu_perf_cfg sm8550_perf_data = {
 	.bw_inefficiency_factor = 120,
 };
 
+static const struct dpu_mdss_version sm8550_mdss_ver = {
+	.core_major_ver = 9,
+	.core_minor_ver = 0,
+};
+
 const struct dpu_mdss_cfg dpu_sm8550_cfg = {
+	.mdss_ver = &sm8550_mdss_ver,
 	.caps = &sm8550_dpu_caps,
 	.ubwc = &sm8550_ubwc_cfg,
 	.mdp = &sm8550_mdp,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 1d150091da9c..98a04a39d333 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -746,6 +746,16 @@ struct dpu_perf_cdp_cfg {
 	bool wr_enable;
 };
 
+/**
+ * struct dpu_mdss_version - DPU's major and minor versions
+ * @core_major_ver: DPU core's major version
+ * @core_minor_ver: DPU core's minor version
+ */
+struct dpu_mdss_version {
+	u8 core_major_ver;
+	u8 core_minor_ver;
+};
+
 /**
  * struct dpu_perf_cfg - performance control settings
  * @max_bw_low         low threshold of maximum bandwidth (kbps)
@@ -796,8 +806,9 @@ struct dpu_perf_cfg {
 /**
  * struct dpu_mdss_cfg - information of MDSS HW
  * This is the main catalog data structure representing
- * this HW version. Contains number of instances,
- * register offsets, capabilities of the all MDSS HW sub-blocks.
+ * this HW version. Contains dpu's major and minor versions,
+ * number of instances, register offsets, capabilities of the
+ * all MDSS HW sub-blocks.
  *
  * @dma_formats        Supported formats for dma pipe
  * @cursor_formats     Supported formats for cursor pipe
@@ -805,6 +816,8 @@ struct dpu_perf_cfg {
  * @mdss_irqs:         Bitmap with the irqs supported by the target
  */
 struct dpu_mdss_cfg {
+	const struct dpu_mdss_version *mdss_ver;
+
 	const struct dpu_caps *caps;
 
 	const struct dpu_ubwc_cfg *ubwc;
-- 
2.40.1

Re: [PATCH v4 1/4] drm/msm/dpu: re-introduce dpu core revision to the catalog

[Dmitry Baryshkov]

On 12/07/2023 03:33, Abhinav Kumar wrote:
> Introduce the dpu core revision back as an entry to the catalog so that
> we can just use dpu revision checks and enable those bits which
> should be enabled unconditionally and not controlled by a catalog
> and also simplify the changes to do something like:
> 
> if (dpu_core_revision > xxxxx && dpu_core_revision < xxxxx)
>     enable the bit;
> 
> Since dpu's major and minor versions are now separate fields, lets
> drop all the DPU_HW_VER macros.

Nit: there are no DPU_HW_VER macros. This should probably be a part of 
changelog.

Other than that:

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> 
> changes in v4:
> 	- removed hex prefix from the revisions
> 	- updated the commit text to move some parts to cover letter
> 	- rebased and added support for sm6125 into this
> 	- introduce struct dpu_mdss_version to hold the core revision
> 
> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
>   .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h  |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h  |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h  |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h  |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h  |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h  |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h  |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h  |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h  |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h  |  6 ++++++
>   .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h    |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h  |  6 ++++++
>   .../drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h  |  6 ++++++
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h  | 17 +++++++++++++++--
>   17 files changed, 111 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 7d87dc2d7b1b..b5fbac55f127 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -315,7 +315,13 @@ static const struct dpu_perf_cfg msm8998_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version msm8998_mdss_ver = {
> +	.core_major_ver = 3,
> +	.core_minor_ver = 0,
> +};
> +
>   const struct dpu_mdss_cfg dpu_msm8998_cfg = {
> +	.mdss_ver = &msm8998_mdss_ver,
>   	.caps = &msm8998_dpu_caps,
>   	.ubwc = &msm8998_ubwc_cfg,
>   	.mdp = &msm8998_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 87459cf40895..8000b870d3a7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -332,7 +332,13 @@ static const struct dpu_perf_cfg sdm845_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sdm845_mdss_ver = {
> +	.core_major_ver = 4,
> +	.core_minor_ver = 0,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sdm845_cfg = {
> +	.mdss_ver = &sdm845_mdss_ver,
>   	.caps = &sdm845_dpu_caps,
>   	.ubwc = &sdm845_ubwc_cfg,
>   	.mdp = &sdm845_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 96c542d620f1..7ce2d69d28f6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -375,7 +375,13 @@ static const struct dpu_perf_cfg sm8150_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sm8150_mdss_ver = {
> +	.core_major_ver = 5,
> +	.core_minor_ver = 0,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sm8150_cfg = {
> +	.mdss_ver = &sm8150_mdss_ver,
>   	.caps = &sm8150_dpu_caps,
>   	.ubwc = &sm8150_ubwc_cfg,
>   	.mdp = &sm8150_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 4edc1060f05c..cea005382456 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -402,7 +402,13 @@ static const struct dpu_perf_cfg sc8180x_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sc8180x_mdss_ver = {
> +	.core_major_ver = 5,
> +	.core_minor_ver = 1,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
> +	.mdss_ver = &sc8180x_mdss_ver,
>   	.caps = &sc8180x_dpu_caps,
>   	.ubwc = &sc8180x_ubwc_cfg,
>   	.mdp = &sc8180x_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> index b3bfb897327b..5fddfcce6288 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> @@ -200,7 +200,13 @@ static const struct dpu_perf_cfg sm6125_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sm6125_mdss_ver = {
> +	.core_major_ver = 5,
> +	.core_minor_ver = 4,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sm6125_cfg = {
> +	.mdss_ver = &sm6125_mdss_ver,
>   	.caps = &sm6125_dpu_caps,
>   	.ubwc = &sm6125_ubwc_cfg,
>   	.mdp = &sm6125_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index f8910dbc1952..893d1271fb71 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -390,7 +390,13 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sm8250_mdss_ver = {
> +	.core_major_ver = 6,
> +	.core_minor_ver = 0,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sm8250_cfg = {
> +	.mdss_ver = &sm8250_mdss_ver,
>   	.caps = &sm8250_dpu_caps,
>   	.ubwc = &sm8250_ubwc_cfg,
>   	.mdp = &sm8250_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 8c046eacec7c..61118f648cbc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -204,7 +204,13 @@ static const struct dpu_perf_cfg sc7180_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sc7180_mdss_ver = {
> +	.core_major_ver = 6,
> +	.core_minor_ver = 2,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sc7180_cfg = {
> +	.mdss_ver = &sc7180_mdss_ver,
>   	.caps = &sc7180_dpu_caps,
>   	.ubwc = &sc7180_ubwc_cfg,
>   	.mdp = &sc7180_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 473cdbace322..c0d7bb930e8a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -136,7 +136,13 @@ static const struct dpu_perf_cfg sm6115_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sm6115_mdss_ver = {
> +	.core_major_ver = 6,
> +	.core_minor_ver = 3,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sm6115_cfg = {
> +	.mdss_ver = &sm6115_mdss_ver,
>   	.caps = &sm6115_dpu_caps,
>   	.ubwc = &sm6115_ubwc_cfg,
>   	.mdp = &sm6115_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index ac716c8dbd7f..11c50aa5034b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -207,7 +207,13 @@ static const struct dpu_perf_cfg sm6350_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sm6350_mdss_ver = {
> +	.core_major_ver = 6,
> +	.core_minor_ver = 4,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sm6350_cfg = {
> +	.mdss_ver = &sm6350_mdss_ver,
>   	.caps = &sm6350_dpu_caps,
>   	.ubwc = &sm6350_ubwc_cfg,
>   	.mdp = &sm6350_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 7d9fdd807695..2182939bc026 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -126,7 +126,13 @@ static const struct dpu_perf_cfg qcm2290_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version qcm2290_mdss_ver = {
> +	.core_major_ver = 6,
> +	.core_minor_ver = 5,
> +};
> +
>   const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
> +	.mdss_ver = &qcm2290_mdss_ver,
>   	.caps = &qcm2290_dpu_caps,
>   	.ubwc = &qcm2290_ubwc_cfg,
>   	.mdp = &qcm2290_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index 5f36f9468853..f0c0aa90f82e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -146,7 +146,13 @@ static const struct dpu_perf_cfg sm6375_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sm6375_mdss_ver = {
> +	.core_major_ver = 6,
> +	.core_minor_ver = 9,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sm6375_cfg = {
> +	.mdss_ver = &sm6375_mdss_ver,
>   	.caps = &sm6375_dpu_caps,
>   	.ubwc = &sm6375_ubwc_cfg,
>   	.mdp = &sm6375_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index b22e6b97c993..2460ced03610 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -383,7 +383,13 @@ static const struct dpu_perf_cfg sm8350_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sm8350_mdss_ver = {
> +	.core_major_ver = 7,
> +	.core_minor_ver = 0,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sm8350_cfg = {
> +	.mdss_ver = &sm8350_mdss_ver,
>   	.caps = &sm8350_dpu_caps,
>   	.ubwc = &sm8350_ubwc_cfg,
>   	.mdp = &sm8350_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 4b2cc62b07ea..a8dea8f27c41 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -252,7 +252,13 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sc7280_mdss_ver = {
> +	.core_major_ver = 7,
> +	.core_minor_ver = 2,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sc7280_cfg = {
> +	.mdss_ver = &sc7280_mdss_ver,
>   	.caps = &sc7280_dpu_caps,
>   	.ubwc = &sc7280_ubwc_cfg,
>   	.mdp = &sc7280_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index ec959f85ae2a..397fe01125dd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -445,7 +445,13 @@ static const struct dpu_perf_cfg sc8280xp_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sc8280xp_mdss_ver = {
> +	.core_major_ver = 8,
> +	.core_minor_ver = 0,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
> +	.mdss_ver = &sc8280xp_mdss_ver,
>   	.caps = &sc8280xp_dpu_caps,
>   	.ubwc = &sc8280xp_ubwc_cfg,
>   	.mdp = &sc8280xp_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 98a4aaef94d2..90a8461911c8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -406,7 +406,13 @@ static const struct dpu_perf_cfg sm8450_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sm8450_mdss_ver = {
> +	.core_major_ver = 8,
> +	.core_minor_ver = 1,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sm8450_cfg = {
> +	.mdss_ver = &sm8450_mdss_ver,
>   	.caps = &sm8450_dpu_caps,
>   	.ubwc = &sm8450_ubwc_cfg,
>   	.mdp = &sm8450_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 7de9eccf9181..c9252528136d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -420,7 +420,13 @@ static const struct dpu_perf_cfg sm8550_perf_data = {
>   	.bw_inefficiency_factor = 120,
>   };
>   
> +static const struct dpu_mdss_version sm8550_mdss_ver = {
> +	.core_major_ver = 9,
> +	.core_minor_ver = 0,
> +};
> +
>   const struct dpu_mdss_cfg dpu_sm8550_cfg = {
> +	.mdss_ver = &sm8550_mdss_ver,
>   	.caps = &sm8550_dpu_caps,
>   	.ubwc = &sm8550_ubwc_cfg,
>   	.mdp = &sm8550_mdp,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 1d150091da9c..98a04a39d333 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -746,6 +746,16 @@ struct dpu_perf_cdp_cfg {
>   	bool wr_enable;
>   };
>   
> +/**
> + * struct dpu_mdss_version - DPU's major and minor versions
> + * @core_major_ver: DPU core's major version
> + * @core_minor_ver: DPU core's minor version
> + */
> +struct dpu_mdss_version {
> +	u8 core_major_ver;
> +	u8 core_minor_ver;
> +};
> +
>   /**
>    * struct dpu_perf_cfg - performance control settings
>    * @max_bw_low         low threshold of maximum bandwidth (kbps)
> @@ -796,8 +806,9 @@ struct dpu_perf_cfg {
>   /**
>    * struct dpu_mdss_cfg - information of MDSS HW
>    * This is the main catalog data structure representing
> - * this HW version. Contains number of instances,
> - * register offsets, capabilities of the all MDSS HW sub-blocks.
> + * this HW version. Contains dpu's major and minor versions,
> + * number of instances, register offsets, capabilities of the
> + * all MDSS HW sub-blocks.
>    *
>    * @dma_formats        Supported formats for dma pipe
>    * @cursor_formats     Supported formats for cursor pipe
> @@ -805,6 +816,8 @@ struct dpu_perf_cfg {
>    * @mdss_irqs:         Bitmap with the irqs supported by the target
>    */
>   struct dpu_mdss_cfg {
> +	const struct dpu_mdss_version *mdss_ver;
> +
>   	const struct dpu_caps *caps;
>   
>   	const struct dpu_ubwc_cfg *ubwc;

-- 
With best wishes
Dmitry

[PATCH v4 2/4] drm/msm/dpu: use dpu core's major version to enable data compress

[Abhinav Kumar]

Instead of using a feature bit to decide whether to enable data
compress or not for DSC use-cases, use dpu core's major version
instead by assigning the enable_compression op based on the
dpu core's major version.

To make this possible pass the struct dpu_mdss_version to
dpu_hw_intf_init().

This will avoid defining feature bits for every bit level details of
registers.

changes in v4:
	- split renaming of enable_compression into another change
	- pass struct dpu_mdss_version to dpu_hw_intf_init() to
	  assign the enable_compression op based on dpu's core revision

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 ++++----
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 ++-
 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 2 +-
 3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 5b0f6627e29b..d766791438e7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -523,7 +523,7 @@ static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)
 }
 
 static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
-		unsigned long cap)
+		unsigned long cap, const struct dpu_mdss_version *mdss_rev)
 {
 	ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine;
 	ops->setup_prg_fetch  = dpu_hw_intf_setup_prg_fetch;
@@ -543,12 +543,12 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
 		ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh;
 	}
 
-	if (cap & BIT(DPU_INTF_DATA_COMPRESS))
+	if (mdss_rev->core_major_ver >= 7)
 		ops->enable_compression = dpu_hw_intf_enable_compression;
 }
 
 struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
-		void __iomem *addr)
+		void __iomem *addr, const struct dpu_mdss_version *mdss_rev)
 {
 	struct dpu_hw_intf *c;
 
@@ -569,7 +569,7 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
 	 */
 	c->idx = cfg->id;
 	c->cap = cfg;
-	_setup_intf_ops(&c->ops, c->cap->features);
+	_setup_intf_ops(&c->ops, c->cap->features, mdss_rev);
 
 	return c;
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 99e21c4137f9..3b5f18dbcb4b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -127,9 +127,10 @@ struct dpu_hw_intf {
  * interface catalog entry.
  * @cfg:  interface catalog entry for which driver object is required
  * @addr: mapped register io address of MDP
+ * @mdss_rev: dpu core's major and minor versions
  */
 struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
-		void __iomem *addr);
+		void __iomem *addr, const struct dpu_mdss_version *mdss_rev);
 
 /**
  * dpu_hw_intf_destroy(): Destroys INTF driver context
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index e333f4eeafc1..4a53e2c931d6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -161,7 +161,7 @@ int dpu_rm_init(struct dpu_rm *rm,
 		struct dpu_hw_intf *hw;
 		const struct dpu_intf_cfg *intf = &cat->intf[i];
 
-		hw = dpu_hw_intf_init(intf, mmio);
+		hw = dpu_hw_intf_init(intf, mmio, cat->mdss_ver);
 		if (IS_ERR(hw)) {
 			rc = PTR_ERR(hw);
 			DPU_ERROR("failed intf object creation: err %d\n", rc);
-- 
2.40.1

Re: [PATCH v4 2/4] drm/msm/dpu: use dpu core's major version to enable data compress

[Dmitry Baryshkov]

On 12/07/2023 03:33, Abhinav Kumar wrote:
> Instead of using a feature bit to decide whether to enable data
> compress or not for DSC use-cases, use dpu core's major version
> instead by assigning the enable_compression op based on the
> dpu core's major version.
> 
> To make this possible pass the struct dpu_mdss_version to
> dpu_hw_intf_init().
> 
> This will avoid defining feature bits for every bit level details of
> registers.
> 
> changes in v4:
> 	- split renaming of enable_compression into another change
> 	- pass struct dpu_mdss_version to dpu_hw_intf_init() to
> 	  assign the enable_compression op based on dpu's core revision
> 
> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 ++++----
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 ++-
>   drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c      | 2 +-
>   3 files changed, 7 insertions(+), 6 deletions(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

[PATCH v4 3/4] drm/msm/dpu: rename enable_compression() to program_intf_cmd_cfg()

[Abhinav Kumar]

Rename the intf's enable_compression() op to program_intf_cmd_cfg()
and allow it to accept a struct intf_cmd_mode_cfg to program
all the bits at once. This can be re-used by widebus later on as
well as it touches the same register.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c |  8 ++++++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c          |  8 +++++---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h          | 11 +++++++++--
 3 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index b856c6286c85..052824eac9f3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -50,6 +50,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
 			to_dpu_encoder_phys_cmd(phys_enc);
 	struct dpu_hw_ctl *ctl;
 	struct dpu_hw_intf_cfg intf_cfg = { 0 };
+	struct intf_cmd_mode_cfg cmd_mode_cfg = {};
 
 	ctl = phys_enc->hw_ctl;
 	if (!ctl->ops.setup_intf_cfg)
@@ -68,8 +69,11 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
 				phys_enc->hw_intf,
 				phys_enc->hw_pp->idx);
 
-	if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression)
-		phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf);
+	if (intf_cfg.dsc != 0)
+		cmd_mode_cfg.data_compress = true;
+
+	if (phys_enc->hw_intf->ops.program_intf_cmd_cfg)
+		phys_enc->hw_intf->ops.program_intf_cmd_cfg(phys_enc->hw_intf, &cmd_mode_cfg);
 }
 
 static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index d766791438e7..7323c713dad1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -513,11 +513,13 @@ static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf,
 
 }
 
-static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)
+static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,
+					     struct intf_cmd_mode_cfg *cmd_mode_cfg)
 {
 	u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2);
 
-	intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
+	if (cmd_mode_cfg->data_compress)
+		intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
 
 	DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2);
 }
@@ -544,7 +546,7 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
 	}
 
 	if (mdss_rev->core_major_ver >= 7)
-		ops->enable_compression = dpu_hw_intf_enable_compression;
+		ops->program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg;
 }
 
 struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 3b5f18dbcb4b..c15f4973de5e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -48,6 +48,11 @@ struct intf_status {
 	u32 line_count;		/* current line count including blanking */
 };
 
+struct intf_cmd_mode_cfg {
+	u8 data_compress;	/* enable data compress between dpu and dsi */
+	/* can be expanded for other programmable bits */
+};
+
 /**
  * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions
  *  Assumption is these functions will be called after clocks are enabled
@@ -70,7 +75,7 @@ struct intf_status {
  * @get_autorefresh:            Retrieve autorefresh config from hardware
  *                              Return: 0 on success, -ETIMEDOUT on timeout
  * @vsync_sel:                  Select vsync signal for tear-effect configuration
- * @enable_compression:         Enable data compression
+ * @program_intf_cmd_cfg:       Program the DPU to interface datapath for command mode
  */
 struct dpu_hw_intf_ops {
 	void (*setup_timing_gen)(struct dpu_hw_intf *intf,
@@ -108,7 +113,9 @@ struct dpu_hw_intf_ops {
 	 */
 	void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay);
 
-	void (*enable_compression)(struct dpu_hw_intf *intf);
+	// Program the datapath between DPU and intf for command mode
+	void (*program_intf_cmd_cfg)(struct dpu_hw_intf *intf,
+				     struct intf_cmd_mode_cfg *cmd_mode_cfg);
 };
 
 struct dpu_hw_intf {
-- 
2.40.1

Re: [PATCH v4 3/4] drm/msm/dpu: rename enable_compression() to program_intf_cmd_cfg()

[Dmitry Baryshkov]

On 12/07/2023 03:33, Abhinav Kumar wrote:
> Rename the intf's enable_compression() op to program_intf_cmd_cfg()
> and allow it to accept a struct intf_cmd_mode_cfg to program
> all the bits at once. This can be re-used by widebus later on as
> well as it touches the same register.
> 
> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c |  8 ++++++--
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c          |  8 +++++---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h          | 11 +++++++++--
>   3 files changed, 20 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index b856c6286c85..052824eac9f3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -50,6 +50,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
>   			to_dpu_encoder_phys_cmd(phys_enc);
>   	struct dpu_hw_ctl *ctl;
>   	struct dpu_hw_intf_cfg intf_cfg = { 0 };
> +	struct intf_cmd_mode_cfg cmd_mode_cfg = {};
>   
>   	ctl = phys_enc->hw_ctl;
>   	if (!ctl->ops.setup_intf_cfg)
> @@ -68,8 +69,11 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
>   				phys_enc->hw_intf,
>   				phys_enc->hw_pp->idx);
>   
> -	if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression)
> -		phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf);
> +	if (intf_cfg.dsc != 0)
> +		cmd_mode_cfg.data_compress = true;
> +
> +	if (phys_enc->hw_intf->ops.program_intf_cmd_cfg)
> +		phys_enc->hw_intf->ops.program_intf_cmd_cfg(phys_enc->hw_intf, &cmd_mode_cfg);
>   }
>   
>   static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index d766791438e7..7323c713dad1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -513,11 +513,13 @@ static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf,
>   
>   }
>   
> -static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)
> +static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,
> +					     struct intf_cmd_mode_cfg *cmd_mode_cfg)
>   {
>   	u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2);
>   
> -	intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
> +	if (cmd_mode_cfg->data_compress)
> +		intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
>   
>   	DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2);
>   }
> @@ -544,7 +546,7 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
>   	}
>   
>   	if (mdss_rev->core_major_ver >= 7)
> -		ops->enable_compression = dpu_hw_intf_enable_compression;
> +		ops->program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg;
>   }
>   
>   struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> index 3b5f18dbcb4b..c15f4973de5e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> @@ -48,6 +48,11 @@ struct intf_status {
>   	u32 line_count;		/* current line count including blanking */
>   };
>   
> +struct intf_cmd_mode_cfg {

My first reaction was that usually all DPU structure names start with 
dpu_. Then I discovered that dpu_hw_intf.h diverges from this useful 
custom. Could you please: fix existing structure struct intf_* names to 
bear the dpu_ prefix. Then this structure can also be named as struct 
dpu_intf_cmd_mode_cfg.

> +	u8 data_compress;	/* enable data compress between dpu and dsi */
> +	/* can be expanded for other programmable bits */

Please drop this comment.

> +};
> +
>   /**
>    * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions
>    *  Assumption is these functions will be called after clocks are enabled
> @@ -70,7 +75,7 @@ struct intf_status {
>    * @get_autorefresh:            Retrieve autorefresh config from hardware
>    *                              Return: 0 on success, -ETIMEDOUT on timeout
>    * @vsync_sel:                  Select vsync signal for tear-effect configuration
> - * @enable_compression:         Enable data compression
> + * @program_intf_cmd_cfg:       Program the DPU to interface datapath for command mode
>    */
>   struct dpu_hw_intf_ops {
>   	void (*setup_timing_gen)(struct dpu_hw_intf *intf,
> @@ -108,7 +113,9 @@ struct dpu_hw_intf_ops {
>   	 */
>   	void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay);
>   
> -	void (*enable_compression)(struct dpu_hw_intf *intf);
> +	// Program the datapath between DPU and intf for command mode

We have been using c99 comments in the code, Moreover, there is already 
description for this field in the comment above, so it can be dropped too.

> +	void (*program_intf_cmd_cfg)(struct dpu_hw_intf *intf,
> +				     struct intf_cmd_mode_cfg *cmd_mode_cfg);
>   };
>   
>   struct dpu_hw_intf {

-- 
With best wishes
Dmitry

Re: [PATCH v4 3/4] drm/msm/dpu: rename enable_compression() to program_intf_cmd_cfg()

[Abhinav Kumar]

On 7/11/2023 5:42 PM, Dmitry Baryshkov wrote:
> On 12/07/2023 03:33, Abhinav Kumar wrote:
>> Rename the intf's enable_compression() op to program_intf_cmd_cfg()
>> and allow it to accept a struct intf_cmd_mode_cfg to program
>> all the bits at once. This can be re-used by widebus later on as
>> well as it touches the same register.
>>
>> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c |  8 ++++++--
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c          |  8 +++++---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h          | 11 +++++++++--
>>   3 files changed, 20 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>> index b856c6286c85..052824eac9f3 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>> @@ -50,6 +50,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
>>               to_dpu_encoder_phys_cmd(phys_enc);
>>       struct dpu_hw_ctl *ctl;
>>       struct dpu_hw_intf_cfg intf_cfg = { 0 };
>> +    struct intf_cmd_mode_cfg cmd_mode_cfg = {};
>>       ctl = phys_enc->hw_ctl;
>>       if (!ctl->ops.setup_intf_cfg)
>> @@ -68,8 +69,11 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
>>                   phys_enc->hw_intf,
>>                   phys_enc->hw_pp->idx);
>> -    if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression)
>> -        phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf);
>> +    if (intf_cfg.dsc != 0)
>> +        cmd_mode_cfg.data_compress = true;
>> +
>> +    if (phys_enc->hw_intf->ops.program_intf_cmd_cfg)
>> +        
>> phys_enc->hw_intf->ops.program_intf_cmd_cfg(phys_enc->hw_intf, 
>> &cmd_mode_cfg);
>>   }
>>   static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx)
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> index d766791438e7..7323c713dad1 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> @@ -513,11 +513,13 @@ static void 
>> dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf,
>>   }
>> -static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx)
>> +static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,
>> +                         struct intf_cmd_mode_cfg *cmd_mode_cfg)
>>   {
>>       u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2);
>> -    intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
>> +    if (cmd_mode_cfg->data_compress)
>> +        intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
>>       DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2);
>>   }
>> @@ -544,7 +546,7 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops 
>> *ops,
>>       }
>>       if (mdss_rev->core_major_ver >= 7)
>> -        ops->enable_compression = dpu_hw_intf_enable_compression;
>> +        ops->program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg;
>>   }
>>   struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h 
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
>> index 3b5f18dbcb4b..c15f4973de5e 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
>> @@ -48,6 +48,11 @@ struct intf_status {
>>       u32 line_count;        /* current line count including blanking */
>>   };
>> +struct intf_cmd_mode_cfg {
> 
> My first reaction was that usually all DPU structure names start with 
> dpu_. Then I discovered that dpu_hw_intf.h diverges from this useful 
> custom. Could you please: fix existing structure struct intf_* names to 
> bear the dpu_ prefix. Then this structure can also be named as struct 
> dpu_intf_cmd_mode_cfg.
> 

Yeah I thought so too .... Ok, I can clean that up in this series and 
rename this.

Ack on the below comments.

>> +    u8 data_compress;    /* enable data compress between dpu and dsi */
>> +    /* can be expanded for other programmable bits */
> 
> Please drop this comment.
> 
>> +};
>> +
>>   /**
>>    * struct dpu_hw_intf_ops : Interface to the interface Hw driver 
>> functions
>>    *  Assumption is these functions will be called after clocks are 
>> enabled
>> @@ -70,7 +75,7 @@ struct intf_status {
>>    * @get_autorefresh:            Retrieve autorefresh config from 
>> hardware
>>    *                              Return: 0 on success, -ETIMEDOUT on 
>> timeout
>>    * @vsync_sel:                  Select vsync signal for tear-effect 
>> configuration
>> - * @enable_compression:         Enable data compression
>> + * @program_intf_cmd_cfg:       Program the DPU to interface datapath 
>> for command mode
>>    */
>>   struct dpu_hw_intf_ops {
>>       void (*setup_timing_gen)(struct dpu_hw_intf *intf,
>> @@ -108,7 +113,9 @@ struct dpu_hw_intf_ops {
>>        */
>>       void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t 
>> encoder_id, u16 vdisplay);
>> -    void (*enable_compression)(struct dpu_hw_intf *intf);
>> +    // Program the datapath between DPU and intf for command mode
> 
> We have been using c99 comments in the code, Moreover, there is already 
> description for this field in the comment above, so it can be dropped too.
> 
>> +    void (*program_intf_cmd_cfg)(struct dpu_hw_intf *intf,
>> +                     struct intf_cmd_mode_cfg *cmd_mode_cfg);
>>   };
>>   struct dpu_hw_intf {
> 

[PATCH v4 4/4] drm/msm/dpu: drop DPU_INTF_DATA_COMPRESS from dpu catalog

[Abhinav Kumar]

Now that all usages of DPU_INTF_DATA_COMPRESS have been replaced
with the dpu core's major revision lets drop DPU_INTF_DATA_COMPRESS
from the catalog completely.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 2522e06c5262..3ff07d7cbf4b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -104,7 +104,7 @@
 	 BIT(DPU_INTF_STATUS_SUPPORTED) | \
 	 BIT(DPU_DATA_HCTL_EN))
 
-#define INTF_SC7280_MASK (INTF_SC7180_MASK | BIT(DPU_INTF_DATA_COMPRESS))
+#define INTF_SC7280_MASK (INTF_SC7180_MASK)
 
 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
 			 BIT(DPU_WB_UBWC) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 98a04a39d333..acfe43f4918c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -181,7 +181,6 @@ enum {
  * @DPU_DATA_HCTL_EN                Allows data to be transferred at different rate
  *                                  than video timing
  * @DPU_INTF_STATUS_SUPPORTED       INTF block has INTF_STATUS register
- * @DPU_INTF_DATA_COMPRESS          INTF block has DATA_COMPRESS register
  * @DPU_INTF_MAX
  */
 enum {
@@ -189,7 +188,6 @@ enum {
 	DPU_INTF_TE,
 	DPU_DATA_HCTL_EN,
 	DPU_INTF_STATUS_SUPPORTED,
-	DPU_INTF_DATA_COMPRESS,
 	DPU_INTF_MAX
 };
 
-- 
2.40.1