From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Komal Bajaj <quic_kbajaj@quicinc.com>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v4 5/6] soc: qcom: Add LLCC support for multi channel DDR
Date: Fri, 23 Jun 2023 16:58:33 +0200 [thread overview]
Message-ID: <b84b2bfc-6f8f-f50f-27b5-52a982ae30f2@linaro.org> (raw)
In-Reply-To: <20230623141806.13388-6-quic_kbajaj@quicinc.com>
On 23.06.2023 16:18, Komal Bajaj wrote:
> Add LLCC support for multi channel DDR configuration
> based on a feature register. Reading DDR channel
> confiuration uses nvmem framework, so select the
> dependency in Kconfig. Without this, there will be
> errors while building the driver with COMPILE_TEST only.
>
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
> drivers/soc/qcom/Kconfig | 2 ++
> drivers/soc/qcom/llcc-qcom.c | 33 ++++++++++++++++++++++++++++++---
> 2 files changed, 32 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> index a491718f8064..cc9ad41c63aa 100644
> --- a/drivers/soc/qcom/Kconfig
> +++ b/drivers/soc/qcom/Kconfig
> @@ -64,6 +64,8 @@ config QCOM_LLCC
> tristate "Qualcomm Technologies, Inc. LLCC driver"
> depends on ARCH_QCOM || COMPILE_TEST
> select REGMAP_MMIO
> + select NVMEM
> + select QCOM_SCM
> help
> Qualcomm Technologies, Inc. platform specific
> Last Level Cache Controller(LLCC) driver for platforms such as,
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 6cf373da5df9..3c29612da1c5 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -12,6 +12,7 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/mutex.h>
> +#include <linux/nvmem-consumer.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> #include <linux/regmap.h>
> @@ -943,6 +944,19 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev,
> return ret;
> }
>
> +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index)
> +{
> + int ret;
> +
> + ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index);
> + if (ret == -ENOENT) {
> + *cfg_index = 0;
> + return 0;
> + }
> +
> + return ret;
> +}
> +
> static int qcom_llcc_remove(struct platform_device *pdev)
> {
> /* Set the global pointer to a error code to avoid referencing it */
> @@ -975,11 +989,13 @@ static int qcom_llcc_probe(struct platform_device *pdev)
> struct device *dev = &pdev->dev;
> int ret, i;
> struct platform_device *llcc_edac;
> - const struct qcom_llcc_config *cfg;
> + const struct qcom_llcc_config *cfg, *entry;
> const struct llcc_slice_config *llcc_cfg;
> u32 sz;
> + u8 cfg_index;
> u32 version;
> struct regmap *regmap;
> + u32 num_entries = 0;
>
> drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
> if (!drv_data) {
> @@ -1040,8 +1056,19 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>
> drv_data->version = version;
>
> - llcc_cfg = cfg[0]->sct_data;
> - sz = cfg[0]->size;
> + ret = qcom_llcc_get_cfg_index(pdev, &cfg_index);
> + if (ret)
> + goto err;
> +
> + for (entry = cfg; entry->sct_data; entry++, num_entries++)
> + ;
> + if (cfg_index >= num_entries || cfg_index < 0) {
cfg_index is an unsigned variable, it can never be < 0
> + ret = -EINVAL;
> + goto err;
> + }
> +
if (cfg_index >= entry->size)? With that, you can also keep the config
entries non-0-terminated in the previous patch, saving a whole lot of RAM.
Konrad
> + llcc_cfg = cfg[cfg_index].sct_data;
> + sz = cfg[cfg_index].size;
>
> for (i = 0; i < sz; i++)
> if (llcc_cfg[i].slice_id > drv_data->max_slices)
next prev parent reply other threads:[~2023-06-23 14:58 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-23 14:18 [PATCH v4 0/6] soc: qcom: llcc: Add support for QDU1000/QRU1000 Komal Bajaj
2023-06-23 14:18 ` [PATCH v4 1/6] dt-bindings: nvmem: sec-qfprom: Add bindings for secure qfprom Komal Bajaj
2023-06-23 16:36 ` Krzysztof Kozlowski
2023-06-26 8:22 ` Komal Bajaj
2023-06-26 8:30 ` Krzysztof Kozlowski
[not found] ` <c8909dcb-143c-c2d7-513d-625e9ce00c0c@quicinc.com>
2023-06-26 9:46 ` Krzysztof Kozlowski
2023-06-26 10:08 ` Komal Bajaj
2023-06-23 14:18 ` [PATCH v4 2/6] dt-bindings: cache: qcom,llcc: Add LLCC compatible for QDU1000/QRU1000 Komal Bajaj
2023-06-23 16:37 ` Krzysztof Kozlowski
2023-06-23 14:18 ` [PATCH v4 3/6] nvmem: sec-qfprom: Add Qualcomm secure QFPROM support Komal Bajaj
2023-06-23 14:53 ` Konrad Dybcio
2023-06-27 8:34 ` Komal Bajaj
2023-06-30 20:03 ` Bjorn Andersson
2023-06-24 1:06 ` kernel test robot
2023-06-30 20:14 ` Bjorn Andersson
2023-06-23 14:18 ` [PATCH v4 4/6] soc: qcom: llcc: Refactor llcc driver to support multiple configuration Komal Bajaj
2023-06-23 14:18 ` [PATCH v4 5/6] soc: qcom: Add LLCC support for multi channel DDR Komal Bajaj
2023-06-23 14:26 ` Dmitry Baryshkov
[not found] ` <db8ea67e-529c-856b-026e-2435a2405f6b@quicinc.com>
2023-06-28 13:14 ` Dmitry Baryshkov
2023-06-30 13:54 ` Komal Bajaj
2023-06-23 14:58 ` Konrad Dybcio [this message]
2023-06-28 8:52 ` Komal Bajaj
2023-06-28 11:13 ` Konrad Dybcio
2023-06-30 13:51 ` Komal Bajaj
2023-06-30 20:40 ` Bjorn Andersson
2023-06-23 14:18 ` [PATCH v4 6/6] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support Komal Bajaj
2023-06-23 14:27 ` Dmitry Baryshkov
2023-06-28 8:53 ` Komal Bajaj
2023-06-23 14:59 ` Konrad Dybcio
2023-06-30 20:45 ` [PATCH v4 0/6] soc: qcom: llcc: Add support for QDU1000/QRU1000 Bjorn Andersson
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