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[83.9.30.30]) by smtp.gmail.com with ESMTPSA id p14-20020a2e9a8e000000b002b58eb44badsm753175lji.106.2023.06.23.07.58.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Jun 2023 07:58:34 -0700 (PDT) Message-ID: Date: Fri, 23 Jun 2023 16:58:33 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v4 5/6] soc: qcom: Add LLCC support for multi channel DDR Content-Language: en-US To: Komal Bajaj , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20230623141806.13388-1-quic_kbajaj@quicinc.com> <20230623141806.13388-6-quic_kbajaj@quicinc.com> From: Konrad Dybcio In-Reply-To: <20230623141806.13388-6-quic_kbajaj@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 23.06.2023 16:18, Komal Bajaj wrote: > Add LLCC support for multi channel DDR configuration > based on a feature register. Reading DDR channel > confiuration uses nvmem framework, so select the > dependency in Kconfig. Without this, there will be > errors while building the driver with COMPILE_TEST only. > > Signed-off-by: Komal Bajaj > --- > drivers/soc/qcom/Kconfig | 2 ++ > drivers/soc/qcom/llcc-qcom.c | 33 ++++++++++++++++++++++++++++++--- > 2 files changed, 32 insertions(+), 3 deletions(-) > > diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig > index a491718f8064..cc9ad41c63aa 100644 > --- a/drivers/soc/qcom/Kconfig > +++ b/drivers/soc/qcom/Kconfig > @@ -64,6 +64,8 @@ config QCOM_LLCC > tristate "Qualcomm Technologies, Inc. LLCC driver" > depends on ARCH_QCOM || COMPILE_TEST > select REGMAP_MMIO > + select NVMEM > + select QCOM_SCM > help > Qualcomm Technologies, Inc. platform specific > Last Level Cache Controller(LLCC) driver for platforms such as, > diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c > index 6cf373da5df9..3c29612da1c5 100644 > --- a/drivers/soc/qcom/llcc-qcom.c > +++ b/drivers/soc/qcom/llcc-qcom.c > @@ -12,6 +12,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -943,6 +944,19 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev, > return ret; > } > > +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u8 *cfg_index) > +{ > + int ret; > + > + ret = nvmem_cell_read_u8(&pdev->dev, "multi-chan-ddr", cfg_index); > + if (ret == -ENOENT) { > + *cfg_index = 0; > + return 0; > + } > + > + return ret; > +} > + > static int qcom_llcc_remove(struct platform_device *pdev) > { > /* Set the global pointer to a error code to avoid referencing it */ > @@ -975,11 +989,13 @@ static int qcom_llcc_probe(struct platform_device *pdev) > struct device *dev = &pdev->dev; > int ret, i; > struct platform_device *llcc_edac; > - const struct qcom_llcc_config *cfg; > + const struct qcom_llcc_config *cfg, *entry; > const struct llcc_slice_config *llcc_cfg; > u32 sz; > + u8 cfg_index; > u32 version; > struct regmap *regmap; > + u32 num_entries = 0; > > drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); > if (!drv_data) { > @@ -1040,8 +1056,19 @@ static int qcom_llcc_probe(struct platform_device *pdev) > > drv_data->version = version; > > - llcc_cfg = cfg[0]->sct_data; > - sz = cfg[0]->size; > + ret = qcom_llcc_get_cfg_index(pdev, &cfg_index); > + if (ret) > + goto err; > + > + for (entry = cfg; entry->sct_data; entry++, num_entries++) > + ; > + if (cfg_index >= num_entries || cfg_index < 0) { cfg_index is an unsigned variable, it can never be < 0 > + ret = -EINVAL; > + goto err; > + } > + if (cfg_index >= entry->size)? With that, you can also keep the config entries non-0-terminated in the previous patch, saving a whole lot of RAM. Konrad > + llcc_cfg = cfg[cfg_index].sct_data; > + sz = cfg[cfg_index].size; > > for (i = 0; i < sz; i++) > if (llcc_cfg[i].slice_id > drv_data->max_slices)