[PATCH v2 11/11] soc: qcom: ice: Allow explicit votes on 'iface' clock for ICE

Harshal Dev
2026-03-10T08:08:19Z

Since Qualcomm inline-crypto engine (ICE) is now a dedicated driver
de-coupled from the QCOM UFS driver, it explicitly votes for its required
clocks during probe. For scenarios where the 'clk_ignore_unused' flag is
not passed on the kernel command line, to avoid potential unclocked ICE
hardware register access during probe the ICE driver should additionally
vote on the 'iface' clock.
Also update the suspend and resume callbacks to handle un-voting and voting
on the 'iface' clock.

Fixes: 2afbf43a4aec6 ("soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
---
drivers/soc/qcom/ice.c | 11 +++++++++++
1 file changed, 11 insertions(+)

diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c
index b203bc685cad..e05dc7b274e0 100644
--- a/drivers/soc/qcom/ice.c
+++ b/drivers/soc/qcom/ice.c
@@ -108,6 +108,7 @@ struct qcom_ice {
void __iomem *base;

struct clk *core_clk;
+ struct clk *iface_clk;
bool use_hwkm;
bool hwkm_init_complete;
u8 hwkm_version;
@@ -316,6 +317,13 @@ int qcom_ice_resume(struct qcom_ice *ice)
err);
return err;
}
+
+ err = clk_prepare_enable(ice->iface_clk);
+ if (err) {
+ dev_err(dev, "failed to enable iface clock (%d)\n",
+ err);
+ return err;
+ }
qcom_ice_hwkm_init(ice);
return qcom_ice_wait_bist_status(ice);
}
@@ -323,6 +331,7 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume);

int qcom_ice_suspend(struct qcom_ice *ice)
{
+ clk_disable_unprepare(ice->iface_clk);
clk_disable_unprepare(ice->core_clk);
ice->hwkm_init_complete = false;

@@ -584,6 +593,8 @@ static struct qcom_ice *qcom_ice_create(struct device *dev,
if (IS_ERR(engine->core_clk))
return ERR_CAST(engine->core_clk);

+ engine->iface_clk = devm_clk_get_optional_enabled(dev, "iface_clk");
+
if (!qcom_ice_check_supported(engine))
return ERR_PTR(-EOPNOTSUPP);

--
2.34.1