From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E1AB334689; Fri, 17 Oct 2025 04:41:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760676100; cv=none; b=hWNGD/mEGaHGNQsiaDuXIz9rNLBP8O+J5FaXrdxLZNHvz5vdtr0iwAg4tu460BaBY0LzGTOM2U4wARJy4HDa9prkVrleLGJnL0jLgAYlGCJ4NzloQaWAeHl7OxGKUGPXkxsSddOctfIGa+CYxTolO/6gjIzOaZcY6gocmcKFbdw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760676100; c=relaxed/simple; bh=KYWPYbj9AgafJeUcobj6pYXOKDICTH/bM9n4lOeI20M=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=mBNn0hE1rC9LEokT8jRPf1CFrvkTwwQAjimgZhtRO0bEn+7kPXp+9XxTXxzHb+97DDtQcxc1fZqjWIoJfFX04eUhwp4vZZRNwTnB/MJ7P6xGTBYW/voDzZOYRhne/Pjaf6zbwcM11NrZaNdbvbiMZy3jRWu2uIngEhfrYfbmJns= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XmLws7r8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XmLws7r8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 51051C4CEE7; Fri, 17 Oct 2025 04:41:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760676100; bh=KYWPYbj9AgafJeUcobj6pYXOKDICTH/bM9n4lOeI20M=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=XmLws7r8GpULkOh63waqJm7oKgNtCNBRmv5zeAjqQD7UyYE9LoRJAk9O+oxS6Jf+g nvfqRPDubwxUdR0hSb9AajRCqamgjPStE3uW7bkWarP2f6GEIHo7S1INwzGU1Fz/Vx KoHtdBnBs/SlYezVMIkvMWBsqYwTxDKUhggD0kAPJ5eWeeGTvaZ1nrfidxW+Zevft5 JeR47JaIVrMnfKg6y1Y19tKpsULsblZNtDo+XD0Pv6zIauXYkUy1S94QFHUwNH+wph Ex0iX7FGggXaJFhBIgRYmRuJX0baubB0fNyjFRtK2GLB1/3OG/odcvgo5jQg0QGU7n ciRwD03hOrE6Q== Message-ID: Date: Fri, 17 Oct 2025 06:41:34 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 02/10] dt-bindings: phy: qcom,qmp-usb: Add Glymur USB UNI PHY compatible To: Wesley Cheng , krzk+dt@kernel.org, conor+dt@kernel.org, konrad.dybcio@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, kishon@kernel.org, vkoul@kernel.org, gregkh@linuxfoundation.org, robh@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251006222002.2182777-1-wesley.cheng@oss.qualcomm.com> <20251006222002.2182777-3-wesley.cheng@oss.qualcomm.com> <00408896-2e25-2dd1-6e6e-2195317ee7fb@oss.qualcomm.com> <14bc2a85-0f1d-3834-9b9c-32654348603a@oss.qualcomm.com> <387c707e-613d-433b-a76d-16ef10dabc59@kernel.org> <2a70f878-269c-1b40-2e8c-77b5851de9a1@oss.qualcomm.com> <99ab26d3-eb44-401d-8a7c-1d9efd2a1a10@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 17/10/2025 02:15, Wesley Cheng wrote: >>> Technically its all handling the same clock branch (CXO), we have the >>> TCSR clkref register that allows us to gate the CXO to the USB PHY, as >> >> >> Ah, exactly. Then clkref is not a clock. You need rather proper clock >> hierarchy. >> >>> CXO is shared across several HW blocks, so it allows us to properly >>> powerdown the PHY even though other clients are voting for CXO on. Then >>> we obviously have to remove our vote to the overall CXO, so that it can >>> potentially be shutdown. >>> >>> Maybe we can rename it to "clkref" for the CXO handle and >>> "clkref_switch" for the TCSRCC handle? >> >> Naming is better, but it is still not correct. This is not independent >> clock signal. It is the same clock. >> > > Hmmm... I guess that's why I kept the same clkref tag, to denote that > its the same clock, but one is a switch/gate for it. Would you happen > to have any suggestions you might have that makes it clearer for > everyone to understand? To me it looks like: |-----| |-----------| |------------------| |clock|------------|TCSRCC gate|-----------|clkref to this dev| |-----| |-----------| |------------------| So you need proper clock controller for TCSR (TCSR Clock Controller, in short TCSRCC, what a surprise!) which will take input, add gate and produce clock for this device. Nothing non-standard, all Qualcomm SoCs have it, every other platform has it in some way. Best regards, Krzysztof