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Tue, 25 Jun 2024 20:21:11 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45PKLAsR028185 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 25 Jun 2024 20:21:10 GMT Received: from [10.71.110.249] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 25 Jun 2024 13:21:10 -0700 Message-ID: Date: Tue, 25 Jun 2024 13:21:09 -0700 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH RFC v2] drm/msm/dpu: Configure DP INTF/PHY selector Content-Language: en-US To: Dmitry Baryshkov CC: Rob Clark , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Bjorn Andersson , , , , References: <20240613-dp-phy-sel-v2-1-99af348c9bae@linaro.org> <0ae0fddb-07f4-3eb9-5a62-0f7f15153452@quicinc.com> <3a5f68fb-2487-bda0-91a1-18ecd414937f@quicinc.com> From: Abhinav Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: r3F2q9oVZ20uuPMlhFK3W9UQ2ALN5SKA X-Proofpoint-ORIG-GUID: r3F2q9oVZ20uuPMlhFK3W9UQ2ALN5SKA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-25_15,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 phishscore=0 mlxlogscore=920 bulkscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406250150 On 6/25/2024 1:20 PM, Dmitry Baryshkov wrote: > On Tue, 25 Jun 2024 at 22:28, Abhinav Kumar wrote: >> >> >> >> On 6/25/2024 12:26 PM, Abhinav Kumar wrote: >>> >>> >>> On 6/24/2024 6:39 PM, Abhinav Kumar wrote: >>>> >>>> >>>> On 6/13/2024 4:17 AM, Dmitry Baryshkov wrote: >>>>> From: Bjorn Andersson >>>>> >>>>> Some platforms provides a mechanism for configuring the mapping between >>>>> (one or two) DisplayPort intfs and their PHYs. >>>>> >>>>> In particular SC8180X provides this functionality, without a default >>>>> configuration, resulting in no connection between its two external >>>>> DisplayPort controllers and any PHYs. >>>>> >>>> >>>> I have to cross-check internally about what makes it mandatory to >>>> program this only for sc8180xp. We were not programming this so far >>>> for any chipset and this register is present all the way from sm8150 >>>> till xe10100 and all the chipsets do not have a correct default value >>>> which makes me think whether this is required to be programmed. >>>> >>>> Will update this thread once I do. >>>> >>> >>> Ok, I checked more. The reason this is mandatory for sc8180xp is the >>> number of controllers is greater than number of PHYs needing this to be >>> programmed. On all other chipsets its a 1:1 mapping. >>> >> >> Correction, number of controllers is < number of PHYs. > > Thanks, I'll c&p your explanation to the commit message if you don't mind. > Yes you can, pls go ahead. >> >>> I am fine with the change once the genmap comment is addressed. >