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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-668d22914ecsm4726697a12.21.2026.03.24.06.00.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Mar 2026 06:00:09 -0700 (PDT) Message-ID: Date: Tue, 24 Mar 2026 14:00:04 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clk: qcom: rcg2: expand frac table for mdss_pixel_clk_src To: Pengyu Luo Cc: Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260321095029.2259489-1-mitltlatltl@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=b+q/I9Gx c=1 sm=1 tr=0 ts=69c28add cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=qC_FGOx9AAAA:8 a=EUspDBNiAAAA:8 a=0E1OWuO-EJLwnSaZFvwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=fsdK_YakeE02zTmptMdW:22 X-Proofpoint-ORIG-GUID: tRXbPtNlTiDim1ZNJA7ze6O049hS88ED X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI0MDEwMiBTYWx0ZWRfXwG8lhqL5o+js hz0mg9ehYtQTd8X+mjOkQQnsjz7kt7MqT/7B7B39LX+nZVc5e1hL9rxpD4PDOM49uTVvB9vFUMR AArrvpFZ0QM9a0mksuHtXoZALb/7OC1wP1KFu1ZoPtuNTMIZkbGsJaVE6xSYgJ+E7AADAVU6Ud4 mMpR14IJ0uFcn7GTYisT1Dcxq0a5wiIYHGHrzegZEfSo1WzoCG5VLWIe9Kj2rR7fQfzFokOADWR LM+hmHNHiLIyV/6WlBl/Au0BJXXPUyjOiy7BREy3cTqj91y/wDGLVH4QrqdG+/AJBNhOno+Ks5C PRWTGJRwBgindca4qjBUc6n8Tic80yXYusy4DmvbDvPYnqAcD7HMi2fArOE38jzW03xsbQVoZlT eWfLBN7FAH2xeITuWjk81bnElCucAycykv2RZKgdia/lY/OAi+yNvuw2dLTNJpDlL1kgN3OUXU8 CdZ7/grb9ihICPYhiNw== X-Proofpoint-GUID: tRXbPtNlTiDim1ZNJA7ze6O049hS88ED X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-24_03,2026-03-23_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 adultscore=0 malwarescore=0 bulkscore=0 suspectscore=0 phishscore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603240102 On 3/24/26 1:56 PM, Pengyu Luo wrote: > On Tue, Mar 24, 2026 at 5:22 PM Konrad Dybcio > wrote: >> >> On 3/23/26 8:23 PM, Dmitry Baryshkov wrote: >>> On Mon, Mar 23, 2026 at 01:54:29PM +0100, Konrad Dybcio wrote: >>>> On 3/21/26 10:50 AM, Pengyu Luo wrote: >>>>> Recently, when testing 10-bit dsi C-PHY panel, clks are different >>>>> from the usual. (dsi0_phy_pll_out_dsiclk's parent is dsi0_pll_bit_clk >>>>> now (dsiclk_sel = 0)) And we failed to set dsiclk's children. >>>>> >>>>> dsi_link_clk_set_rate_6g: Set clk rates: pclk=172992000, byteclk=108120000 >>>>> >>>>> byteclk was set first to 108120000, so the vco rate was set to >>>>> 108120000 * 7 * 1 * 1 = 756840000. When we was trying to set >>>>> 172992000 on mdss_pixel_clk_src later. >>>>> >>>>> Since there was no matched ratio, we failed to set it. And dsiclk >>>>> divider ratio was set to 15:1 (wrong cached register value 0xf and >>>>> didn't update), we finally got 50455997, apparently wrong. >>>>> >>>>> dsi0vco_clk 1 1 0 756839941 >>>>> dsi0_pll_out_div_clk 1 1 0 756839941 >>>>> dsi0_pll_post_out_div_clk 0 0 0 216239983 >>>>> dsi0_pll_bit_clk 2 2 0 756839941 >>>>> dsi0_phy_pll_out_dsiclk 2 2 0 50455997 >>>>> disp_cc_mdss_pclk1_clk_src 1 1 0 50455997 >>>>> dsi0_pll_by_2_bit_clk 0 0 0 378419970 >>>>> dsi0_phy_pll_out_byteclk 2 2 0 108119991 >>>>> disp_cc_mdss_byte1_clk_src 2 2 0 108119991 >>>>> >>>>> Downstream clk_summary shows the mdss_pixel_clk_src support the >>>>> ratio(35:16) >>>>> >>>>> dsi0_phy_pll_out_dsiclk 2 2 0 378420000 >>>>> disp_cc_mdss_pclk1_clk_src 1 1 0 172992000 >>>>> dsi0_phy_pll_out_byteclk 2 2 0 108120000 >>>>> disp_cc_mdss_byte1_clk_src 2 2 0 108120000 >>>>> >>>>> After checking downstream source, 15:4 also seems to be supported, >>>>> add them two. >>>> >>>> I don't see that, not even in the newest releases.. Is there even a reason >>>> we have to list these divider pairs in the first place? >>> >>> https://git.codelinaro.org/clo/la/kernel/qcom/-/commit/f7aec4359448d25c8a8d21ad8e8733d61f6b69ab >> >> Ahh branching.. >> >>> We need those dividers to correctly program pclk RCG2 clocks. >> >> I would assume that's the case, but perhaps the real answer is "because we >> don't want to try all possible combinations" >> > > So you meant the pixel clk can support any ratio actually, and just > common ratio pairs are listed? That is interesting. I don't know about pixel specifically, but generally RCG2 clocks can do any rate, only limited by the register width, see: drivers/clk/qcom/clk-rcg2.c : calc_rate() Konrad