From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 463931A7270; Fri, 13 Dec 2024 08:10:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734077455; cv=none; b=gCI/jzasxYURhQaQT9gH8L3y2AR0i60mzGHdAEOvAKmePGFZkgvB0sRfKM+YWgz4w6SWIHmjWoxpB2LxqvXvYGu2cqWwlRUuzEM6I97kcXGwOUXQ8OM0LN3Z/r2T5w4dHU+n7Z9HamFUFXZxWB66Vk79kN6I9FrDP1cU43twdoY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734077455; c=relaxed/simple; bh=Aom1UMzrOBOqk2LYfiZr6r1pt5xBSVA3BVftJnNAVFI=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=rr4EX1Q+AgM1dEgDAwY0wgpTxzK1ij8moVXX7UTsxiWwGN0EbEvM+eI2sjte4s/pTYacUC4+X/uKInWe/wzyytGzkQaIAFBpgAkQgNltK1Mdma4gnTdDu6G9RA7iZzBMjmB/auOUQLgKoJSehjK+57ldwAWwrr01uN8IEEKPpe4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dXKaIOHd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dXKaIOHd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 992E1C4CED0; Fri, 13 Dec 2024 08:10:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1734077454; bh=Aom1UMzrOBOqk2LYfiZr6r1pt5xBSVA3BVftJnNAVFI=; h=Date:Subject:To:References:From:In-Reply-To:From; b=dXKaIOHdtDcWY750RYj0T+FcJWOBC+B6ltV5WHrJsnQ+HPVESxMxHuNrx1lqJ7kGP 1yY2KbdZOovz6ZrZnWj27M2CdJw9u7aTVIoY0QdwunpnVB3WvsUaDqrCulNoyehMHU 5aHgeG3uIdTbC7PmWHWj2s61j61XiS+uSy6iPJnYJFXwKSGfDqsXt+jwuh9Spy2xej AnKzDDHRqhsMz/Njn/u2xkk+q0E/1H0qz+8Spvpy+9b2yRx198sjKr0YX/p5N7mEvI 4/gwap9MJ0Aw6/K2LgTBeRRTCNrPKOaDxWS4UqFaNtXmyf2939wuEdv2ZlGMDx9Qdi TB/WglcnT/tdA== Message-ID: Date: Fri, 13 Dec 2024 09:10:48 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add industrial mezzanine To: Sahil Chandna , kernel@quicinc.com, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, quic_nkumarsi@quicinc.com, quic_akdwived@quicinc.com, quic_kkotecha@quicinc.com References: <20241206065156.2573-1-quic_chandna@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 06/12/2024 07:51, Sahil Chandna wrote: > The industrial mezzanine kit enhances the capabilities of QCS6490 > rb3gen2 core kit. Add support for industrial mezzanine board. > > Signed-off-by: Sahil Chandna > --- > arch/arm64/boot/dts/qcom/Makefile | 3 ++ > .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 44 +++++++++++++++++++ > 2 files changed, 47 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index 6ca8db4b8afe..6fe5a5ccd950 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -111,6 +111,9 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb > + > +qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo I don't see your finial overlay being applied. > + > dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso > new file mode 100644 > index 000000000000..74f2f782d166 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso > @@ -0,0 +1,44 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > +/* > + > +/dts-v1/; > +/plugin/; > + > +#include "pm7250b.dtsi" > +#include "sc7280.dtsi" > + > +&pm7250b_gpios { > + gpio5_tpm_dig_out { It does not look like you tested the DTS against bindings. Please run `make dtbs_check W=1` (see Documentation/devicetree/bindings/writing-schema.rst or https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ for instructions). > + gpio5_dig_out_default: gpio5_dig_out_default { Please follow DTS coding style. > + pins = "gpio5"; > + function = "normal"; > + power-source = <1>; > + output-high; > + input-disable; > + bias-pull-up; > + qcom,drive-strength = <3>; > + }; > + }; > +}; > + > +&qupv3_id_1 { > + status = "okay"; > +}; > + > +&spi11 { > + status = "okay"; > + > + st33htpm0: st33htpm@0 { Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > + compatible = "st,st33htpm-spi"; > + reg = <0>; > + spi-max-frequency = <20000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&gpio5_dig_out_default>; > + status="okay"; Drop > + }; > +}; > -- > 2.17.1 Best regards, Krzysztof