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Fri, 16 Aug 2024 08:34:25 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47G8YOfd025426 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Aug 2024 08:34:24 GMT Received: from [10.217.216.152] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 16 Aug 2024 01:34:20 -0700 Message-ID: Date: Fri, 16 Aug 2024 14:04:17 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490 To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , "Stephen Boyd" , Krzysztof Kozlowski , Rob Herring , "Conor Dooley" CC: , , , , References: <20240531102252.26061-1-quic_tdas@quicinc.com> <20240531102252.26061-3-quic_tdas@quicinc.com> <6aad6a71-dd2f-4682-91ea-835357342ba1@linaro.org> <2800ce74-44ea-444b-b00f-e07bbfdd4415@quicinc.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4HQbZmvXJLlG0qlNB7mwO_8l1_1F5KlG X-Proofpoint-ORIG-GUID: 4HQbZmvXJLlG0qlNB7mwO_8l1_1F5KlG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_18,2024-08-15_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 malwarescore=0 spamscore=0 phishscore=0 mlxlogscore=728 priorityscore=1501 clxscore=1015 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408160061 On 6/18/2024 6:52 PM, Konrad Dybcio wrote: > > > On 6/10/24 12:19, Taniya Das wrote: >> >> >> On 6/7/2024 3:00 PM, Konrad Dybcio wrote: >>> On 31.05.2024 12:22 PM, Taniya Das wrote: >>>> On the QCM6490 boards the LPASS firmware controls the complete clock >>>> controller functionalities. But the LPASS resets are required to be >>>> controlled from the high level OS. The Audio SW driver should be >>>> able to >>>> assert/deassert the audio resets as required. Thus in clock driver add >>>> support for the same. >>>> >>>> Signed-off-by: Taniya Das >>>> --- >>> >>> Please stop ignoring my comments without responding. >>> >>> https://lore.kernel.org/all/c1d07eff-4832-47d9-8598-aa6709b465ff@linaro.org/ >>> >> >> Sorry about that, it was not intentional. I had posted the v2 and >> decided to split as it was delaying the other changes in the older >> series which had more functional fixes. >> >> >> Picking your comments from the old series. >> >> --------------------------------- >>  > -    clk_zonda_pll_configure(&lpass_audio_cc_pll, regmap, >> &lpass_audio_cc_pll_config); >>  > +    if (!of_property_read_bool(pdev->dev.of_node, >> "qcom,adsp-skip-pll")) { >> >> Big no-no. >> -------------------------------- >> >> Yes, I have already moved away from it and introduced a new probe to >> support the subset of functionality on QCM6490. >> >> >> ------------------------ >>  > +        /* PLL settings */ >>  > +        regmap_write(regmap, 0x4, 0x3b); >>  > +        regmap_write(regmap, 0x8, 0xff05); >> >> Model these properly and use the abstracted clock (re)configuration >> functions. >> Add the unreachable clocks to `protected-clocks = <>` and make sure >> that the >> aforementioned configure calls check if the PLL was really registered. >> --------------------------- >> >> These were made for alignment of code, but existing approach was not >> touched. > > That's not purely cosmetic, this now falls into the compatible-specific > if-condition, which was my issue. > >> >> --------------------- >> >>  > +    lpass_audio_cc_sc7280_regmap_config.name = "lpassaudio_cc_reset"; >> >> Ugh.. are these really not contiguous, or were the register ranges >> misrepresented from >> the start? >> >>  > +    lpass_audio_cc_sc7280_regmap_config.max_register = 0xc8; >> >> Provide the real size of the block in .max_register instead, >> unconditionally >> ----------------- >> >> This had a little history behind this approach. During the driver >> development the ask was to avoid duplicating same descriptors and >> update runtime what is possible. That is the reason to update it >> runtime. The max register size is 0xC8 for resets functionality usage >> for High level OS. > > What I mean is that, the register region size is constant for a given > piece of > hardware. Whether Linux can safely access it or not, doesn't matter. The > regmap_size value can just reflect the width of the region (and so > should the > device tree). > I understand the concern you have. I have introduced a separate regmap config for the LPASS resets which will have the required region size. -- Thanks & Regards, Taniya Das.