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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8f6ecadb27sm147972666b.63.2026.02.12.03.30.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Feb 2026 03:30:03 -0800 (PST) Message-ID: Date: Thu, 12 Feb 2026 12:30:00 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/4] soc: qcom: ice: Add OPP-based clock scaling support for ICE To: Abhinaba Rakshit , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Neeraj Soni , Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org References: <20260211-enable-ufs-ice-clock-scaling-v5-0-221c520a1f2e@oss.qualcomm.com> <20260211-enable-ufs-ice-clock-scaling-v5-2-221c520a1f2e@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260211-enable-ufs-ice-clock-scaling-v5-2-221c520a1f2e@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=DtlbOW/+ c=1 sm=1 tr=0 ts=698db9be cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=cMzz2QcylWOBvAN0VsUA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjEyMDA4NSBTYWx0ZWRfXz8uHZls2w1PI bkjUsoVDm5vgyW23yE4z/afcpTE5ULyFH92dOGA4328VtUknhEJLk+OExKV3iX3iU9y3SQZFbMM j55fmOqrlREjUq56VxgXhE0XnUSLVXc21Zz8T7JqrwnaacQ8Be1GyPUXLa5ZofO9SA/KCxAlxJx fSjMkLwmUvREQEJ66u1I01kP3iW7IvAgSoqpVoaXYxXr6G2in1e9RX+4ZfSIntK+JctKjYASEUk YU/uR/tAYVBl3kwY6nmL4ko1NwapmhUZlCkvm/mVuLmWxO05ltLZFfteMDkB+kx3AZqaa3FwEyv MaWctnGJI+cPUczF/avZQTZLoCr1hvKtOuXBrat/yMS6PuVbZKbJOj6SNHvLxc1kGG8SL8SNP+A 4VRbzuK/DhZPfgilbUDue75TopLuLw1Uyub+OJgy4ZfwJO35j9QBgs1xx2w4dzKMFZn+iC6/azq E/JGIjNiIWkD6i9Ah4g== X-Proofpoint-ORIG-GUID: PotL_6TMToWGBlHtCArSFx3Sf1qfhCLj X-Proofpoint-GUID: PotL_6TMToWGBlHtCArSFx3Sf1qfhCLj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-12_03,2026-02-11_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 suspectscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602120085 On 2/11/26 10:47 AM, Abhinaba Rakshit wrote: > Register optional operation-points-v2 table for ICE device > and aquire its minimum and maximum frequency during ICE > device probe. > > Introduce clock scaling API qcom_ice_scale_clk which scale ICE > core clock based on the target frequency provided and if a valid > OPP-table is registered. Use flags (if provided) to decide on > the rounding of the clock freq against OPP-table. Incase no flags > are provided use default behaviour (CEIL incase of scale_up and FLOOR > incase of ~scale_up). Disable clock scaling if OPP-table is not > registered. > > When an ICE-device specific OPP table is available, use the PM OPP > framework to manage frequency scaling and maintain proper power-domain > constraints. > > Also, ensure to drop the votes in suspend to prevent power/thermal > retention. Subsequently restore the frequency in resume from > core_clk_freq which stores the last ICE core clock operating frequency. > > Signed-off-by: Abhinaba Rakshit > --- [...] > +/** > + * qcom_ice_scale_clk() - Scale ICE clock for DVFS-aware operations > + * @ice: ICE driver data > + * @target_freq: requested frequency in Hz > + * @scale_up: If @flags is 0, choose ceil (true) or floor (false) > + * @flags: Rounding policy (ICE_CLOCK_ROUND_*); overrides @scale_up > + * > + * Clamps @target_freq to the OPP range (min/max), selects an OPP per rounding > + * policy, then applies it via dev_pm_opp_set_rate() (including voltage/PD > + * changes). > + * > + * Return: 0 on success; -EOPNOTSUPP if no OPP table; or error from > + * dev_pm_opp_set_rate()/OPP lookup. > + */ > +int qcom_ice_scale_clk(struct qcom_ice *ice, unsigned long target_freq, > + bool scale_up, unsigned int flags) > +{ > + int ret; > + unsigned long ice_freq = target_freq; > + struct dev_pm_opp *opp; Reverse-Christmas-tree ordering would be neat > + > + if (!ice->has_opp) > + return -EOPNOTSUPP; > + > + /* Clamp the freq to max if target_freq is beyond supported frequencies */ > + if (ice->max_freq && target_freq >= ice->max_freq) { > + ice_freq = ice->max_freq; > + goto scale_clock; > + } > + > + /* Clamp the freq to min if target_freq is below supported frequencies */ > + if (ice->min_freq && target_freq <= ice->min_freq) { > + ice_freq = ice->min_freq; > + goto scale_clock; > + } The OPP framework won't let you overclock the ICE if this is what these checks are about. Plus the clk framework will perform rounding for you too > + > + switch (flags) { Are you going to use these flags? Currently they're dead code > + case ICE_CLOCK_ROUND_CEIL: > + opp = dev_pm_opp_find_freq_ceil_indexed(ice->dev, &ice_freq, 0); You never use the index (hardcoded to 0) > + break; > + case ICE_CLOCK_ROUND_FLOOR: > + opp = dev_pm_opp_find_freq_floor_indexed(ice->dev, &ice_freq, 0); > + break; > + default: > + if (scale_up) > + opp = dev_pm_opp_find_freq_ceil_indexed(ice->dev, &ice_freq, 0); > + else > + opp = dev_pm_opp_find_freq_floor_indexed(ice->dev, &ice_freq, 0); Is this distinction necessary? Konrad