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[83.9.29.144]) by smtp.gmail.com with ESMTPSA id z6-20020ac24186000000b004edc0fc3c35sm884804lfh.5.2023.04.22.05.02.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 22 Apr 2023 05:02:58 -0700 (PDT) Message-ID: Date: Sat, 22 Apr 2023 14:02:57 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH] arm64: dts: qcom: Add BLSP DMAs for I2C Content-Language: en-US To: Luca Weiss , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230422-msm8953-blsp-dma-v1-1-0024801bb587@z3ntu.xyz> From: Konrad Dybcio In-Reply-To: <20230422-msm8953-blsp-dma-v1-1-0024801bb587@z3ntu.xyz> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 22.04.2023 13:39, Luca Weiss wrote: > MSM8953 has two DMA controllers for the various I2C, SPI and UART > busses. Add the nodes and configure all the I2C nodes so that the driver > can use the DMA. > > Signed-off-by: Luca Weiss > ---Reviewed-by: Konrad Dybcio Konrad > arch/arm64/boot/dts/qcom/msm8953.dtsi | 48 +++++++++++++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi > index 602cb188a635..c9b589353918 100644 > --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi > @@ -1274,6 +1274,19 @@ opp-200000000 { > }; > }; > > + blsp1_dma: dma-controller@7884000 { > + compatible = "qcom,bam-v1.7.0"; > + reg = <0x07884000 0x1f000>; > + interrupts = ; > + clocks = <&gcc GCC_BLSP1_AHB_CLK>; > + clock-names = "bam_clk"; > + num-channels = <12>; > + #dma-cells = <1>; > + qcom,ee = <0>; > + qcom,num-ees = <4>; > + qcom,controlled-remotely; > + }; > + > uart_0: serial@78af000 { > compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; > reg = <0x078af000 0x200>; > @@ -1292,6 +1305,8 @@ i2c_1: i2c@78b5000 { > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, > <&gcc GCC_BLSP1_AHB_CLK>; > + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; > + dma-names = "tx", "rx"; > > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&i2c_1_default>; > @@ -1310,6 +1325,8 @@ i2c_2: i2c@78b6000 { > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, > <&gcc GCC_BLSP1_AHB_CLK>; > + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; > + dma-names = "tx", "rx"; > > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&i2c_2_default>; > @@ -1328,6 +1345,9 @@ i2c_3: i2c@78b7000 { > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, > <&gcc GCC_BLSP1_AHB_CLK>; > + dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; > + dma-names = "tx", "rx"; > + > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&i2c_3_default>; > pinctrl-1 = <&i2c_3_sleep>; > @@ -1345,6 +1365,9 @@ i2c_4: i2c@78b8000 { > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, > <&gcc GCC_BLSP1_AHB_CLK>; > + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; > + dma-names = "tx", "rx"; > + > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&i2c_4_default>; > pinctrl-1 = <&i2c_4_sleep>; > @@ -1355,6 +1378,19 @@ i2c_4: i2c@78b8000 { > status = "disabled"; > }; > > + blsp2_dma: dma-controller@7ac4000 { > + compatible = "qcom,bam-v1.7.0"; > + reg = <0x07ac4000 0x1f000>; > + interrupts = ; > + clocks = <&gcc GCC_BLSP2_AHB_CLK>; > + clock-names = "bam_clk"; > + num-channels = <12>; > + #dma-cells = <1>; > + qcom,ee = <0>; > + qcom,num-ees = <4>; > + qcom,controlled-remotely; > + }; > + > i2c_5: i2c@7af5000 { > compatible = "qcom,i2c-qup-v2.2.1"; > reg = <0x07af5000 0x600>; > @@ -1362,6 +1398,9 @@ i2c_5: i2c@7af5000 { > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, > <&gcc GCC_BLSP2_AHB_CLK>; > + dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; > + dma-names = "tx", "rx"; > + > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&i2c_5_default>; > pinctrl-1 = <&i2c_5_sleep>; > @@ -1379,6 +1418,9 @@ i2c_6: i2c@7af6000 { > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, > <&gcc GCC_BLSP2_AHB_CLK>; > + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; > + dma-names = "tx", "rx"; > + > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&i2c_6_default>; > pinctrl-1 = <&i2c_6_sleep>; > @@ -1396,6 +1438,9 @@ i2c_7: i2c@7af7000 { > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, > <&gcc GCC_BLSP2_AHB_CLK>; > + dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; > + dma-names = "tx", "rx"; > + > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&i2c_7_default>; > pinctrl-1 = <&i2c_7_sleep>; > @@ -1413,6 +1458,9 @@ i2c_8: i2c@7af8000 { > clock-names = "core", "iface"; > clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, > <&gcc GCC_BLSP2_AHB_CLK>; > + dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; > + dma-names = "tx", "rx"; > + > pinctrl-names = "default", "sleep"; > pinctrl-0 = <&i2c_8_default>; > pinctrl-1 = <&i2c_8_sleep>; > > --- > base-commit: 347e9b4e41bfff51993807962eb1082f6d8ab439 > change-id: 20230422-msm8953-blsp-dma-1174277859f2 > > Best regards,