From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>,
agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
sboyd@kernel.org, linus.walleij@linaro.org,
catalin.marinas@arm.com, will@kernel.org, shawnguo@kernel.org,
arnd@arndb.de, dmitry.baryshkov@linaro.org,
marcel.ziswiler@toradex.com, nfraprado@collabora.com,
robimarko@gmail.com, quic_gurus@quicinc.com,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V2 8/9] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support
Date: Tue, 31 Jan 2023 20:26:17 +0100 [thread overview]
Message-ID: <c031fad0-8f3b-60dc-9429-7bd78ae8a2d0@linaro.org> (raw)
In-Reply-To: <20230130114702.20606-9-quic_kathirav@quicinc.com>
On 30/01/2023 12:47, Kathiravan Thirumoorthy wrote:
> From: Kathiravan T <quic_kathirav@quicinc.com>
>
> Add initial device tree support for the Qualcomm IPQ5332 SoC and
> MI01.2 board.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> + sdhc: mmc@7804000 {
> + compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
> +
> + interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&xo_board>;
> + clock-names = "iface", "core", "xo";
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
No, our discussion did not finish. These are not properties of the SoC
in most cases. Why do you say there are part of the SoC? Is your SoC
coming with the same memory? Memory embedded in the SoC, not in the
board? If yes, the status is incorrect.
> + max-frequency = <192000000>;
Same
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-01-31 19:26 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-30 11:46 [PATCH V2 0/9] Add minimal boot support for IPQ5332 Kathiravan Thirumoorthy
2023-01-30 11:46 ` [PATCH V2 1/9] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl Kathiravan Thirumoorthy
2023-01-31 19:31 ` Krzysztof Kozlowski
2023-01-30 11:46 ` [PATCH V2 2/9] pinctrl: qcom: Introduce IPQ5332 TLMM driver Kathiravan Thirumoorthy
2023-01-30 11:46 ` [PATCH V2 3/9] clk: qcom: Add STROMER PLUS PLL type for IPQ5332 Kathiravan Thirumoorthy
2023-01-30 11:46 ` [PATCH V2 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC Kathiravan Thirumoorthy
2023-01-31 19:28 ` Krzysztof Kozlowski
2023-01-31 21:06 ` Stephen Boyd
2023-01-30 11:46 ` [PATCH V2 6/9] dt-bindings: qcom: add ipq5332 boards Kathiravan Thirumoorthy
2023-01-31 19:29 ` Krzysztof Kozlowski
2023-01-30 11:47 ` [PATCH V2 7/9] dt-bindings: firmware: qcom,scm: document IPQ5332 SCM Kathiravan Thirumoorthy
2023-01-30 11:47 ` [PATCH V2 8/9] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support Kathiravan Thirumoorthy
2023-01-30 12:25 ` Konrad Dybcio
2023-02-01 5:37 ` Kathiravan T
2023-01-31 19:26 ` Krzysztof Kozlowski [this message]
2023-02-01 5:40 ` Kathiravan T
2023-01-30 11:47 ` [PATCH V2 9/9] arm64: defconfig: Enable IPQ5332 SoC base configs Kathiravan Thirumoorthy
2023-01-31 19:27 ` [PATCH V2 0/9] Add minimal boot support for IPQ5332 Krzysztof Kozlowski
2023-02-01 5:43 ` Kathiravan T
[not found] ` <20230130114702.20606-6-quic_kathirav@quicinc.com>
2023-01-31 21:09 ` [PATCH V2 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC Stephen Boyd
2023-02-01 5:45 ` Kathiravan T
2023-02-01 5:46 ` Kathiravan T
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=c031fad0-8f3b-60dc-9429-7bd78ae8a2d0@linaro.org \
--to=krzysztof.kozlowski@linaro.org \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=arnd@arndb.de \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=marcel.ziswiler@toradex.com \
--cc=mturquette@baylibre.com \
--cc=nfraprado@collabora.com \
--cc=quic_gurus@quicinc.com \
--cc=quic_kathirav@quicinc.com \
--cc=robh+dt@kernel.org \
--cc=robimarko@gmail.com \
--cc=sboyd@kernel.org \
--cc=shawnguo@kernel.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox