From: Krzysztof Kozlowski <krzk@kernel.org>
To: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com>,
manivannan.sadhasivam@linaro.org, alim.akhtar@samsung.com,
avri.altman@wdc.com, bvanassche@acm.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, James.Bottomley@HansenPartnership.com,
martin.petersen@oracle.com, agross@kernel.org
Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
quic_narepall@quicinc.com, quic_nitirawa@quicinc.com
Subject: Re: [PATCH V1 2/3] arm64: dts: qcom: sm8650: Add ICE algorithm entries
Date: Tue, 29 Oct 2024 12:23:12 +0100 [thread overview]
Message-ID: <c0e96797-ae44-4e19-9775-ff9ee01e4d67@kernel.org> (raw)
In-Reply-To: <75589588-ed41-42f6-b7fa-c6f0359ba4cd@quicinc.com>
On 29/10/2024 12:06, Ram Kumar Dwivedi wrote:
>
>
> On 06-Oct-24 2:02 PM, Krzysztof Kozlowski wrote:
>> On 05/10/2024 08:43, Ram Kumar Dwivedi wrote:
>>> There are three algorithms supported for inline crypto engine:
>>> Floor based, Static and Instantaneous algorithm.
>>>
>>> Add ice algorithm entries and enable instantaneous algorithm
>>> by default.
>>>
>>> Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
>>> Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
>>> Co-developed-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>>> Signed-off-by: Ram Kumar Dwivedi <quic_rdwivedi@quicinc.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 19 +++++++++++++++++++
>>> 1 file changed, 19 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>>> index 9d9bbb9aca64..56a7ca6a3af4 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>>> @@ -2590,6 +2590,25 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>> #reset-cells = <1>;
>>>
>>> status = "disabled";
>>> +
>>> + ice_cfg: ice-config {
>>> + alg1 {
>>> + alg-name = "alg1";
>>> + rx-alloc-percent = <60>;
>>> + status = "disabled";
>>> + };
>>> +
>>> + alg2 {
>>> + alg-name = "alg2";
>>> + status = "disabled";
>>> + };
>>> +
>>> + alg3 {
>>> + alg-name = "alg3";
>>> + num-core = <28 28 15 13>;
>>> + status = "ok";
>>
>> NAK. This has so many issues... First, describes OS policy. Second,
>> there is no "ok".
>>
> Hi Krzysztof,
> I have updated the status to "okay" in latest patchset
Still no. Why this node needs it?
> and updated the alg-name with actual allocator name.
Please wrap your replies according to mailing list style.
But anyway, all your algs sound like OS policy.
> I have already mentioned default allocator as instantaneous. Sorry, I did not understand OS policy comment, could you please explain?
This looks like OS policy, OS choice. DT does not describe such things.
Best regards,
Krzysztof
next prev parent reply other threads:[~2024-10-29 11:23 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-05 6:43 [PATCH V1 0/3] Add support for multiple ICE algorithms Ram Kumar Dwivedi
2024-10-05 6:43 ` [PATCH V1 1/3] dt-bindings: ufs: qcom: Document ice configuration table Ram Kumar Dwivedi
2024-10-05 14:24 ` Rob Herring (Arm)
2024-10-29 10:55 ` Ram Kumar Dwivedi
2024-10-05 14:37 ` Rob Herring
2024-10-05 19:15 ` Eric Biggers
2024-10-29 11:08 ` Ram Kumar Dwivedi
2024-10-06 8:31 ` Krzysztof Kozlowski
2024-10-05 6:43 ` [PATCH V1 2/3] arm64: dts: qcom: sm8650: Add ICE algorithm entries Ram Kumar Dwivedi
2024-10-06 8:32 ` Krzysztof Kozlowski
2024-10-29 11:06 ` Ram Kumar Dwivedi
2024-10-29 11:23 ` Krzysztof Kozlowski [this message]
2024-10-05 6:43 ` [PATCH V1 3/3] scsi: ufs: qcom: Add support for multiple ICE algorithms Ram Kumar Dwivedi
2024-10-05 19:33 ` Christophe JAILLET
2024-10-29 11:10 ` Ram Kumar Dwivedi
2024-10-06 7:14 ` kernel test robot
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