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Tue, 29 Apr 2025 02:01:57 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53T21uue021861 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Apr 2025 02:01:56 GMT Received: from [10.71.110.123] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Apr 2025 19:01:56 -0700 Message-ID: Date: Mon, 28 Apr 2025 19:01:55 -0700 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/5] drm/msm/dpu: remove DSC feature bit for PINGPONG on SDM630 To: Dmitry Baryshkov , Rob Clark , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , =?UTF-8?B?QmFybmFiw6FzIEN6w6ltw6Fu?= , Konrad Dybcio CC: , , , References: <20250301-dpu-fix-catalog-v2-0-498271be8b50@linaro.org> <20250301-dpu-fix-catalog-v2-5-498271be8b50@linaro.org> Content-Language: en-US From: Abhinav Kumar In-Reply-To: <20250301-dpu-fix-catalog-v2-5-498271be8b50@linaro.org> Content-Type: text/plain; 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Drop the DPU_PINGPONG_DSC feature bit > from the PINGPONG's feature mask, replacing PINGPONG_SDM845_MASK with > BIT(DPU_PINGPONG_DITHER). > > Fixes: 7204df5e7e68 ("drm/msm/dpu: add support for SDM660 and SDM630 platforms") > Reported-by: Abhinav Kumar > Signed-off-by: Dmitry Baryshkov > > --- > Note, Konrad pointed out that vendor DT doesn't define DIPTHER support > for this platform, however I believe this is because support for this > platform predates DITHER support in the vendor kernels. > --- Yes this is correct. This chipset has dither support in ping-pong. > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h > index 3aed9aa4c533f167ece7b4a5eb84fe49c4929df5..99c0f824d8f00474812bde12e7d83ba3de1834f1 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h > @@ -115,14 +115,14 @@ static const struct dpu_pingpong_cfg sdm630_pp[] = { > { > .name = "pingpong_0", .id = PINGPONG_0, > .base = 0x70000, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > + .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), > }, { > .name = "pingpong_2", .id = PINGPONG_2, > .base = 0x71000, .len = 0xd4, > - .features = PINGPONG_SDM845_MASK, > + .features = BIT(DPU_PINGPONG_DITHER), > .sblk = &sdm845_pp_sblk, > .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), > Reviewed-by: Abhinav Kumar