From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D155C64E8A for ; Mon, 30 Nov 2020 15:19:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2065A20725 for ; Mon, 30 Nov 2020 15:19:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="jTvLO3i4" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726761AbgK3PTJ (ORCPT ); Mon, 30 Nov 2020 10:19:09 -0500 Received: from m42-4.mailgun.net ([69.72.42.4]:33715 "EHLO m42-4.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725849AbgK3PTJ (ORCPT ); Mon, 30 Nov 2020 10:19:09 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1606749528; h=Content-Transfer-Encoding: Content-Type: In-Reply-To: MIME-Version: Date: Message-ID: From: References: Cc: To: Subject: Sender; bh=YXAsOYOUrsciF9dQdYiRD/IJQ5xmG9rmdFJE2earlRA=; b=jTvLO3i48svU4iyiHTJAQTDdr5KQHOJZ5d7GuwtpSc0Eq6znT278DMhUsGWhng0s74oELc2y 7VCiaza7An8xQuXuuYayHRS4ydFEsVTSzc2Rb5AQEkNZ9AV8jrz7q+GLhdImHREIQPTvgXla ritM9frSkVT2kF2dprXezmDnVeg= X-Mailgun-Sending-Ip: 69.72.42.4 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n03.prod.us-east-1.postgun.com with SMTP id 5fc50d3bfa67d9becf5af123 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Mon, 30 Nov 2020 15:18:19 GMT Sender: jhugo=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 1A991C43460; Mon, 30 Nov 2020 15:18:19 +0000 (UTC) Received: from [10.226.59.216] (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jhugo) by smtp.codeaurora.org (Postfix) with ESMTPSA id E3C54C433C6; Mon, 30 Nov 2020 15:18:17 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E3C54C433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=jhugo@codeaurora.org Subject: Re: [PATCH v2] bus: mhi: Ensure correct ring update ordering with memory barrier To: Loic Poulain , Manivannan Sadhasivam Cc: Hemant Kumar , linux-arm-msm References: <1606403201-5656-1-git-send-email-loic.poulain@linaro.org> <20201128060331.GH3077@thinkpad> From: Jeffrey Hugo Message-ID: Date: Mon, 30 Nov 2020 08:18:17 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 11/30/2020 1:18 AM, Loic Poulain wrote: > On Sat, 28 Nov 2020 at 07:03, Manivannan Sadhasivam > wrote: >> >> On Thu, Nov 26, 2020 at 04:06:41PM +0100, Loic Poulain wrote: >>> The ring element data, though being part of coherent memory, still need >>> to be performed before updating the ring context to point to this new >>> element. That can be guaranteed with a memory barrier (dma_wmb). >>> >>> Signed-off-by: Loic Poulain >>> --- >>> v2: fix comment style >>> >>> drivers/bus/mhi/core/main.c | 7 +++++++ >>> 1 file changed, 7 insertions(+) >>> >>> diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c >>> index 67188ea..ea39df0 100644 >>> --- a/drivers/bus/mhi/core/main.c >>> +++ b/drivers/bus/mhi/core/main.c >>> @@ -111,7 +111,14 @@ void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl, >>> dma_addr_t db; >>> >>> db = ring->iommu_base + (ring->wp - ring->base); >>> + >>> + /* >>> + * Writes to the new ring element must be visible to the hardware >>> + * before letting h/w know there is new element to fetch. >>> + */ >>> + dma_wmb(); >>> *ring->ctxt_wp = db; >> >> As Jeff pointed out, the barrier should come after updating ctxt_wp. > > Actually, device can poll for the write pointer (e.g. in burst mode), > so we need to be sure the element data are written before writing this > write pointer (since it can be accessed at any time on device side, > not only after doorbell). > > I think that what jeff pointed is that we also need to ensure that > write pointer is also updated before we ring the doorbell (doorbell > mode), but this is implicitly done by the MMIO writing (using > writeX()) of the doorbell register.(cf > https://www.kernel.org/doc/Documentation/memory-barriers.txt). If we are using the version of the writeX API that includes a barrier, then that would be sufficient. -- Jeffrey Hugo Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.