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Fri, 06 Dec 2024 20:17:37 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B6KHael018454 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 6 Dec 2024 20:17:36 GMT Received: from [10.110.95.46] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 6 Dec 2024 12:17:31 -0800 Message-ID: Date: Fri, 6 Dec 2024 12:17:29 -0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/9] drm/msm/dpu: Add SM6150 support To: Fange Zhang , Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Krishna Manikandan" , Bjorn Andersson , Konrad Dybcio , "Catalin Marinas" , Will Deacon , Li Liu , Xiangxu Yin CC: , , , , , References: <20241122-add-display-support-for-qcs615-platform-v3-0-35252e3a51fe@quicinc.com> <20241122-add-display-support-for-qcs615-platform-v3-5-35252e3a51fe@quicinc.com> Content-Language: en-US From: Abhinav Kumar In-Reply-To: <20241122-add-display-support-for-qcs615-platform-v3-5-35252e3a51fe@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: yj9fXnaj5lnOP6LN3qd6Slds2MgrbGF- X-Proofpoint-GUID: yj9fXnaj5lnOP6LN3qd6Slds2MgrbGF- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412060152 On 11/22/2024 1:56 AM, Fange Zhang wrote: > From: Li Liu > > Add definitions for the display hardware used on the Qualcomm SM6150 > platform. > > Signed-off-by: Li Liu > Signed-off-by: Fange Zhang > --- > .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 263 +++++++++++++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > 4 files changed, 266 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h > new file mode 100644 > index 0000000000000000000000000000000000000000..e8b7f694b885d69a9bbfaa85b0faf0c7af677a75 > --- /dev/null > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h > @@ -0,0 +1,263 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DPU_5_3_SM6150_H > +#define _DPU_5_3_SM6150_H > + > + > +static const struct dpu_sspp_cfg sm6150_sspp[] = { > + { > + .name = "sspp_0", .id = SSPP_VIG0, > + .base = 0x4000, .len = 0x1f0, > + .features = VIG_SDM845_MASK, This is not correct. Smartdma is supported on this chipset on both Vig and DMA SSPPs. Please use VIG_SDM845_MASK_SDMA and DMA_SDM845_MASK_SDMA respectively. > + .sblk = &dpu_vig_sblk_qseed3_2_4, > + .xin_id = 0, > + .type = SSPP_TYPE_VIG, > + .clk_ctrl = DPU_CLK_CTRL_VIG0, > + }, { > + .name = "sspp_8", .id = SSPP_DMA0, > + .base = 0x24000, .len = 0x1f0, > + .features = DMA_SDM845_MASK, > + .sblk = &dpu_dma_sblk, > + .xin_id = 1, > + .type = SSPP_TYPE_DMA, > + .clk_ctrl = DPU_CLK_CTRL_DMA0, > + }, { > + .name = "sspp_9", .id = SSPP_DMA1, > + .base = 0x26000, .len = 0x1f0, > + .features = DMA_SDM845_MASK, > + .sblk = &dpu_dma_sblk, > + .xin_id = 5, > + .type = SSPP_TYPE_DMA, > + .clk_ctrl = DPU_CLK_CTRL_DMA1, > + }, { > + .name = "sspp_10", .id = SSPP_DMA2, > + .base = 0x28000, .len = 0x1f0, > + .features = DMA_CURSOR_SDM845_MASK_SDMA, > + .sblk = &dpu_dma_sblk, > + .xin_id = 9, > + .type = SSPP_TYPE_DMA, > + .clk_ctrl = DPU_CLK_CTRL_DMA2, > + }, { > + .name = "sspp_11", .id = SSPP_DMA3, > + .base = 0x2a000, .len = 0x1f0, > + .features = DMA_CURSOR_SDM845_MASK_SDMA, > + .sblk = &dpu_dma_sblk, > + .xin_id = 13, > + .type = SSPP_TYPE_DMA, > + .clk_ctrl = DPU_CLK_CTRL_DMA3, > + }, > +}; > +